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S70GL02GT12FHIV10

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
Document Number: 002-13915 Rev. *C Page 13 of 21
S70GL02GT
7. BGA Package Capacitance
Notes
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25 °C, f = 1.0 MHz.
8. Thermal Resistance
9. Data Integrity
9.1 Erase Endurance
Note:
1. Each write command to a nonvolatile register causes a P/E cycle on the entire nonvolatile register array. OTP bits and registers internally reside in a separate array
that is not P/E cycled.
9.2 Data Retention
Contact Cypress Sales or an FAE representative for additional information regarding data integrity.
Table 8. BGA Package Capacitance
Parameter Symbol Parameter Description Typ Max Unit
C
IN
Input capacitance 9 11 pF
C
OUT
Output capacitance 7 9 pF
A26 Highest order address 5 6 pF
CE# Separated control pin 4 5 pF
OE# Separated control pin 4 5 pF
WE# Separated control pin 7 8 pF
WP# Separated control pin 5 6 pF
RESET# Separated control pin 39 41 pF
RY/BY# Separated control pin 4 5 pF
Table 9. Thermal Resistance
Parameter Description LSH064 Unit
Theta JA Thermal resistance (junction to ambient) 29 °C/W
Table 10. Erase Endurance
Parameter Minimum Unit
Program/Erase cycles per main flash array sectors 100K P/E cycle
Program/Erase cycles per PPB array or nonvolatile register array (1) 100K P/E cycle
Table 11. Data Retention
Parameter Test Conditions Minimum Time Unit
Data Retention Time
1K Program/Erase Cycles 20 Years
10K Program/Erase Cycles 2 Years
100K Program/Erase Cycles .2 Years
Document Number: 002-13915 Rev. *C Page 14 of 21
S70GL02GT
10. Device ID and Common Flash Interface (ID-CFI) ASO Map
The Device ID portion of the ASO (word locations 0h to 0Fh) provides manufacturer ID, device ID, Sector Protection State, and basic
feature set information for the device.
ID-CFI Location 02h displays sector protection status for the sector selected by the sector address (SA) used in the ID-CFI enter
command. To read the protection status of more than one sector it is necessary to exit the ID ASO and enter the ID ASO using the
new SA. The access time to read location 02h is always t
ACC
and a read of this location requires CE# to go High before the read and
return Low to initiate the read (asynchronous read access). Page mode read between location 02h and other ID locations is not
supported. Page mode read between ID locations other than 02h is supported.
Table 12. ID (Autoselect) Address Map
Description Address (x16) Address (x8) Read Data
Manufacture ID (SA) + 0000h (SA) + 0000h 0001h
Device ID (SA) + 0001h (SA) + 0002h 227Eh
Protection Verification (SA) + 0002h (SA) + 0004h
Sector Protection State (1= Sector protected, 0= Sector unprotected). To read a different SA
protection state only a new SA needs to be given.
Indicator Bits (SA) + 0003h (SA) + 0006h
For S70GL02Gt highest address sector protect: XX3Fh = Not Factory Locked
XXBFh = Factory Locked
For S70GL02GT lowest address sector protect: XX2Fh = Not Factory Locked
XXAFh = Factory Locked
DQ15-DQ08 = 1 (Reserved)
DQ7 - Factory Locked Secure Silicon Region
1 = Locked
0 = Not Locked
DQ6 - Customer Locked Secure Silicon Region
1 = Locked
0 = Not Locked
DQ5 = 1 (Reserved)
DQ4 - WP# Protects
0 = lowest address Sector
1 = highest address Sector
DQ3 - DQ0 = 1 (Reserved)
RFU
(SA) + 0004h (SA) + 0008h Reserved
(SA) + 0005h (SA) + 000Ah Reserved
(SA) + 0006h (SA) + 000Ch Reserved
(SA) + 0007h (SA) + 000Eh Reserved
(SA) + 0008h (SA) + 0010h Reserved
(SA) + 0009h (SA) + 0012h Reserved
(SA) + 000Ah (SA) + 0014h Reserved
(SA) + 000Bh (SA) + 0016h Reserved
Lower Software Bits (SA) + 000Ch (SA) + 0018h
Bit 0 - Status Register Support
1 = Status Register Supported
0 = Status Register not supported
Bit 1 - DQ polling Support
1 = DQ bits polling supported
0 = DQ bits polling not supported
Bit 3-2 - Command Set Support
11 = reserved
10 = reserved
01 = Reduced Command Set
00 = Classic Command set
Bits 4-15 - Reserved = 0
Upper Software Bits (SA) + 000Dh (SA) + 001Ah Reserved
Device ID (SA) + 000Eh (SA) + 001Ch 2248h = 2 Gb
Device ID (SA) + 000Fh (SA) + 000Eh 2201h
Document Number: 002-13915 Rev. *C Page 15 of 21
S70GL02GT
Table 13. CFI Query Identification String
Word Address Data Description
(SA) + 0010h
(SA) + 0011h
(SA) + 0012h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
(SA) + 0013h
(SA) + 0014h
0002h
0000h
Primary OEM Command Set
(SA) + 0015h
(SA) + 0016h
0040h
0000h
Address for Primary Extended Table
(SA) + 0017h
(SA) + 0018h
0000h
0000h
Alternate OEM Command Set
(00h = none exists)
(SA) + 0019h
(SA) + 001Ah
0000h
0000h
Address for Alternate OEM Extended Table
(00h = none exists)
Table 14. CFI System Interface String
Word Address Data Description
(SA) + 001Bh 0027h V
CC
Min (erase/program) (D7-D4: volts, D3-D0: 100 mV)
(SA) + 001Ch 0036h V
CC
Max (erase/program) (D7-D4: volts, D3-D0: 100 mV)
(SA) + 001Dh 0000h V
PP
Min voltage (00h = no V
PP
pin present)
(SA) + 001Eh 0000h V
PP
Max voltage (00h = no V
PP
pin present)
(SA) + 001Fh 0008h Typical timeout per single word write 2
N
µs
(SA) + 0020h 0009h
Typical timeout for max
multi-byte program, 2
N
µs
(00h = not supported)
(SA) + 0021h 000Ah Typical timeout per individual block erase 2
N
ms
(SA) + 0022h 0015h (2 Gb) Typical timeout for full chip erase 2
N
ms (00h = not supported)
(SA) + 0023h
0002h (85°C)
0003h (105°C)
Max timeout for single word write 2
N
times typical
(SA) + 0024h
0001h (85°C)
0002h (105°C)
Max timeout for buffer write 2
N
times typical
(SA) + 0025h 0002h Max timeout per individual block erase 2
N
times typical
(SA) + 0026h 0002h
Max timeout for full chip erase 2
N
times typical
(00h = not supported)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

S70GL02GT12FHIV10

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NOR Flash Nor
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