Document Number: 002-13915 Rev. *C Page 6 of 21
2. Input/Output Descriptions and Logic Symbol
Table 3 identifies the input and output package connections provided on the device.
Table 3. Input/Output Descriptions
Symbol Type Description
DQ14–DQ0 I/O Data inputs and outputs.
DQ15/A-1 Input/Output
DQ15: Data inputs and outputs.
A-1: LSB address input in byte mode.
CE# Input Chip Enable. At V
IL
, selects the device for data transfer with the host memory controller.
OE# Input
Output Enable. At V
IL
, causes outputs to be actively driven. At V
IH
, causes outputs to be high
impedance (High-Z).
WE# Input
Write Enable. At V
IL
, indicates data transfer from the host to device. At V
IH
, indicates data
transfer is from the device to host.
A26-A0 Input Address lines for S29GL02GT.
V
CC
Supply Core power supply.
V
IO
Supply Versatile I/O power supply.
V
SS
Supply Power supplies ground.
RY/BY#
Output — open
drain
Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At V
IL
, the
device is actively engaged in an embedded algorithm such as erasing or programming. At
High-Z, the device is ready for read or a new command write — requires an external pull-up
resistor to detect the High-Z state. Multiple devices may have their
RY/BY# outputs tied together to detect when all devices are ready.
BYTE# Input
Selects data bus width. At V
IL
, the device is in byte configuration and data I/O pins DQ7-DQ0
are active and DQ15/A-1 becomes the LSB address input. At V
IH
, the device is in word
configuration and data I/O pins DQ15-DQ0 are active.
RESET# Input
Hardware Reset. At V
IL
, causes the device to reset control logic to its standby state, ready for
reading array data.
WP# Input
Write Protect. At V
IL
, disables program and erase functions in the highest address 64-kword
(128-KB) sector of the device. At V
IH
, the sector is not protected. WP# has an internal pull-up;
When unconnected WP# is at V
IH
.
NC No Connect
Not Connected internally. The pin/ball location may be used in the printed circuit board (PCB)
as part of a routing channel.
DNU Reserved
Do Not Use. Reserved for use by Cypress. The pin/ball is connected internally. The input has
an internal pull-down resistance to V
SS
. The pin/ball can be left open or tied to V
SS
on the PCB.
RFU No Connect
Reserved for Future Use. Not currently connected internally but the pin/ball location should be
left unconnected and unused by the PCB routing channel for future compatibility. The pin/ball
may be used by a signal in the future.
