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LE25W81QES00-AH-1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
LE25W81QE
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10
3. Write Enable
Before performing any of the operations listed below, the device must be placed in the write enable state. Operation
is the same as for setting status register WEN to "1", and the state is enabled by inputting the write enable command.
"Figure 8 Write Enable" shows the timing waveforms when the write enable operation is performed. The write
enable command consists only of the first bus cycle, and it is initiated by inputting (06h).
Small sector erase, sector erase, chip erase
Page program
Status register write
4. Write Disable
The write disable command sets status register WEN to "0" to prohibit unintentional writing. "Figure 9 Write
Disable" shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is
initiated by inputting (04h). The write disable state (WEN "0") is exited by setting WEN to "1" using the write
enable command (06h).
Figure 8 Write Enable Figure 9 Write Disable
5. Power-down
The power-down command sets all the commands, with the exception of the silicon ID read command and the
command to exit from power-down, to the acceptance prohibited state (power-down). "Figure 10 Power-down"
shows the timing waveforms. The power-down command consists only of the first bus cycle, and it is initiated by
inputting (B9h). However, a power-down command issued during an internal write operation will be ignored. The
power-down state is exited using the power-down exit command (power-down is exited also when one bus cycle or
more of the silicon ID read command (ABh) has been input). "Figure 11 Exiting from Power-down" shows the
timing waveforms of the power-down exit command.
Figure 10 Power-down Figure 11 Exiting from Power-down
SCK
SI
High Impedance
SO
CS
06h
0 1 2 3
4 5 6 7
Mode3
Mode0
8CLK
SCK
SI
High Impedance
SO
CS
04h
0 1 2 3
4 5 6 7
Mode3
Mode0
8CLK
SCK
SI
High Impedance
SO
CS
B9h
0 1 2 3
4 5 6 7
Mode3
Mode0
8CLK
SCK
SI
High Impedance
SO
CS
A
Bh
0 1 2 3
4 5 6 7
Mode3
Mode0
8CLK
t
PRB
t
DP
Power down
mode
Power down
mode
LE25W81QE
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11
6. Small Sector Erase
Small sector erase is an operation that sets the memory cell data in any small sector to "1". A small sector consists of
4Kbytes. "Figure 12 Small Sector Erase" shows the timing waveforms, and Figure 21 shows a small sector erase
flowchart. The small sector erase command consists of the first through fourth bus cycles, and it is initiated by
inputting the 24-bit addresses following (D7h or 20h). Addresses A19 to A12 are valid, and Addresses A23 to A20
are "don't care". After the command has been input, the internal erase operation starts from the rising CS
edge, and it
ends automatically by the control exercised by the internal timer. Erase end can also be detected using status register
RDY
.
Figure 12 Small Sector Erase
7. Sector Erase
Sector erase is an operation that sets the memory cell data in any sector to "1". A sector consists of 64K bytes.
"Figure 13 Sector Erase" shows the timing waveforms, and Figure 21 shows a sector erase flowchart. The sector
erase command consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses
following (D8h). Addresses A19 to A16 are valid, and Addresses A23 to A20 are "don't care". After the command
has been input, the internal erase operation starts from the rising CS
edge, and it ends automatically by the control
exercised by the internal timer. Erase end can also be detected using status register RDY
.
Figure 13 Sector Erase
SO
Self-timed
Erase Cycle
SCK
SI
High Impedance
CS
t
SSE
Add. D7h or 20h Add. Add.
15
0 1 2 3
4 5 6 7 8 2316 24 31
Mode3
Mode0
8CLK
SCK
SI
High Impedance
SO
CS
t
SE
Self-timed
Erase Cycle
Add. D8h Add. Add.
15
0 1 2 3
4 5 6 7 8 2316 24 31
Mode3
Mode0
8CLK
LE25W81QE
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12
8. Chip Erase
Chip erase is an operation that sets the memory cell data in all the sectors to "1". "Figure 14 Chip Erase" shows the
timing waveforms, and Figure 21 shows a chip erase flowchart. The chip erase command consists only of the first
bus cycle, and it is initiated by inputting (C7h). After the command has been input, the internal erase operation starts
from the rising CS
edge, and it ends automatically by the control exercised by the internal timer. Erase end can also
be detected using status register RDY
.
Figure 14 Chip Erase
9. Page Program
Page program is an operation that programs any number of bytes from 1 to 256 bytes within the same sector page
(page addresses: A19 to A8). Before initiating page program, the data on the page concerned must be erased using
small sector erase, sector erase, or chip erase. "Figure 15 Page Program" shows the page program timing waveforms,
and Figure 22 shows a page program flowchart. After the falling CS
, edge, the command (02H) is input followed by
the 24-bit addresses. Addresses A19 to A0 are valid. The program data is then loaded at each rising clock edge until
the rising CS
edge, and data loading is continued until the rising CS edge. If the data loaded has exceeded 256 bytes,
the 256 bytes loaded last are programmed. The program data must be loaded in 1-byte increments, and the program
operation is not performed at the rising CS
edge occurring at any other timing. The page programming time of 0.3
ms (typ) when programming 256 bytes (1 page) at one time makes for fast data writing.
Figure 15 Page Program
SCK
SI
High Impedance
SO
CS
t
CHE
Self-timed
Erase Cycle
C7h
0 1 2 3 4 5 6 7
Mode3
Mode0
8CLK
t
PP
Self-timed
Program Cycle
SCK
SI
High Impedance
SO
CS
PD
A
dd.
A
dd. 02h
A
dd. PD
150 1 2 3 4 5 6 7 8 2316 24 31 32 39 40 47
Mode3
Mode0
8CLK
PD
2079
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

LE25W81QES00-AH-1

Mfr. #:
Buy LE25W81QES00-AH-1
Manufacturer:
ON Semiconductor
Description:
NOR Flash S-FLASH MEMORY(8M)
Lifecycle:
New from this manufacturer.
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