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10. Silicon ID Read
Silicon ID read is an operation that reads the manufacturer code and device code information. "Table 6 Silicon ID
codes table" lists the silicon ID codes. The silicon ID read command is not accepted during writing.
Two methods are used for silicon ID reading. The first method involves inputting the 9Fh command: the setting is
completed with only the first bus cycle input, and in subsequent bus cycles the manufacturer code 62h and device
code 26h are repeatedly output in succession so long as the clock input is continued. Refer to "Figure 16-a Silicon
ID read 1" for the waveforms.
The second method involves inputting the ABh command. This command consists of the first through fourth bus
cycles, and the silicon ID can be read when 16 dummy bits and an 8-bit address are input after (ABh). When address
A0 is "0", the manufacturer code 62h is read in the fifth bus cycle, and the device code 26h is read in the sixth bus
cycle. "Figure 16-b Silicon ID read 2" shows the timing waveforms. If, after the manufacturer code or device code
has been read, the SCK input is continued, the manufacturer code and device code are output alternately with each
bus cycle. When address A0 is "1", reading starts with device code 26h in the fifth bus cycle.
Table 6 Silicon ID Codes
Address
A0
Output Code
Manufacturer code 0 62h
Device code 1 27h
The data is output starting with the falling clock edge of the fourth bus cycle bit 0, and silicon ID reading ends at the
rising CS
edge.
Figure 16-a Silicon ID Read 1
Figure 16-b Silicon ID Read 2
N N+1 N
CS
High Impedance
SiID SiID SiID
SCK
SO
SI
9Fh
15
MSB MSB MSB
0 1 2 3
4 5 6 7 8 2316
8CLK
Mode0
Mode3
N N+1 N
CS
High Impedance
SiID SiID SiID
SCK
SO
SI
A
Bh
A
dd. X X
15
MSB MSB MSB
0 1 2 3
4 5 6 7 8 2316 24 31 39 47
8CLK
Mode0
Mode3
32 40
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11. Hold Function
Using the HOLD
pin, the hold function suspends serial communication (it places it in the hold status). "Figure 17
HOLD
" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the
logic level of SCK is low, and it exits from the hold status at the rising HOLD
edge. When the logic level of SCK is
high, HOLD
must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is
exited and serial communication is reset at the rising CS
edge. In the hold status, the SO output is in the high-
impedance state, and SI and SCK are "don't care".
Figure 17 HOLD
12. Power-on
In order to protect against unintentional writing, CS
must be kept at V
DD
At power-on. After power-on, the supply
voltage has stabilized at 2.70 V or higher, wait for 100 s (t
PU
_READ) before inputting the command to start a read
operation. Similarly, wait for 10 ms (t
PU
_WRITE) after the voltage has stabilized before inputting the command to
start a write operation.
Figure 18 Power-on Timing
CS
HOLD
SCK
SO
A
ctive
HOLD
A
ctive
t
HH
t
HS
t
HLZ
t
HHZ
High Impedance
t
HH
t
HS
V
DD
(Max)
V
DD
(Min)
V
DD
Chip selection not Allowed
0V
t
PU
_WRITE
t
PU
_READ
Program, Erase and Write Command not Allowed
Read Access Allowed
Full Access Allowed
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13. Hardware Data Protection
In order to protect against unintentional writing at power-on, the LE25W81QE incorporates a power-on reset
function. The following conditions must be met in order to ensure that the power reset circuit will operate stably.
No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period.
Figure 19 Power-down Timing
14. Software Data Protection
The LE25W81QE eliminates the possibility of unintentional operations by not recognizing commands under the
following conditions.
When a write command is input and the rising CS
edge timing is not in a bus cycle (8 CLK units of SCK)
When the page program data is not in 1-byte increments
When the status register write command is input for 2 bus cycles or more
15. Decoupling Capacitor
A 0.1 F ceramic capacitor must be provided to each device and connected between V
DD
and V
SS
in order to
ensure that the device will operate stably.
V
DD
(Max)
V
DD
(Min)
V
DD
No Device Access Allowed
0V
vBOT
t
PU
_WRITE
t
PU
_READ
t
PD
Program, Erase and Write Command not Allowed

LE25W81QES00-AH-1

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
NOR Flash S-FLASH MEMORY(8M)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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