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LE25W81QES00-AH-1

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LE25W81QE
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7
2. Status Registers
The status registers hold the operating and setting statuses inside the device, and this information can be read (status
register read) and the protect information can be rewritten (status register write). There are 8 bits in total, and "Table
3 Status registers" gives the significance of each bit.
Table 3 Status Registers
Bit Name Logic Function Power-on Time Information
Bit0
RDY
0 Ready
0
1 Erase/Program
Bit1 WEN
0 Write disabled
0
1 Write enabled
Bit2 BP0
0
Block protect information
See status register descriptions on BP0, BP1, and BP2.
Nonvolatile information
1
Bit3 BP1
0
Nonvolatile information
1
Bit4 BP2
0
Nonvolatile information
1
Bit5
Reserved bits
0
Bit6 0
Bit7 SRWP
0 Status register write enabled
Nonvolatile information
1 Status register write disabled
2-1. Status register read
The contents of the status registers can be read using the status register read command. This command can be
executed even during the following operations.
Small sector erase, sector erase, chip erase
Page program
Status register write
"Figure 6 Status Register Read" shows the timing waveforms of status register read. Consisting only of the first bus
cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the
clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit 7) is the
first to be output, and each time one clock is input, all the other bits up to RDY
(bit 0) are output in sequence,
synchronized to the falling clock edge. If the clock input is continued after RDY
(bit 0) has been output, the data is
output by returning to the bit (SRWP) that was first output, after which the output is repeated for as long as the clock
input is continued. The data can be read by the status register read command at any time (even during a program or
erase cycle).
Figure 6 Status Register Read
CS
SCK
SI
SO
MSB MSB MSB
05h
DATA DATA
High Impedance
8 3 2 1 0 7 6 5 4 15
23
Mode 3
Mode 0
8CLK
16
DATA
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8
2-2. Status register write
The information in status registers BP0, BP1, BP2 and SRWP can be rewritten using the status register write
command. RDY
, WEN, bit 5, and bit 6 are read-only bits and cannot be rewritten. The information in bits BP0, BP1,
BP2, and SRWP is stored in the non-volatile memory, and when it is written in these bits, the contents are retained
even at power-down. "Figure 7 Status Register Write" shows the timing waveforms of status register write, and
Figure 20 shows a status register write flowchart. Consisting of the first and second bus cycles, the status register
write command initiates the internal write operation at the rising CS
edge after the data has been input following
(01h). Erase and program are performed automatically inside the device by status register write so that erasing or
other processing is unnecessary before executing the command. By the operation of this command, the information
in bits BP0, BP1, BP2, and SRWP can be rewritten. Since bits RDY
(bit 0), WEN (bit 1), 4, 5, and 6 of the status
register cannot be written, no problem will arise if an attempt is made to set them to any value when rewriting the
status register. Status register write ends can be detected by RDY
of status register read. Information in the status
registers can be rewritten 1,000 times (min). To initiate status register write, the logic level of the WP
pin must be
set high and status register WEN must be set to "1".
Figure 7 Status Register Write
2-3. Contents of each status register
RDY
(bit 0)
The RDY
register is for detecting the write (program, erase and status register write) end. When it is "1", the device
is in a busy state, and when it is "0", it means that write is completed.
t
SRW
Self-timed
Write Cycle
SCK
SI
High Impedance
SO
CS
DATA 01h
150 1 2 3 4 5 6 7 8
Mode3
Mode0
8CLK
WP
t
WPH
t
WPS
LE25W81QE
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9
WEN (bit 1)
The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will
not perform the write operation even if the write command is input. If it is set to "1", the device can perform write
operations in any area that is not block-protected.
WEN can be controlled using the write enable and write disable commands. By inputting the write enable command
(06h), WEN can be set to "1"; by inputting the write disable command (04h), it can be set to "0." In the following
states, WEN is automatically set to "0" in order to protect against unintentional writing.
At power-on
Upon completion of small sector erase, sector erase or chip erase
Upon completion of page program
Upon completion of status register write
* If a write operation has not been performed inside the LE25W81QE because, for instance, the command input for
any of the write operations (small sector erase, sector erase, chip erase, page program, or status register write) has
failed or a write operation has been performed for a protected address, WEN will retain the status established prior
to the issue of the command concerned. Furthermore, its state will not be changed by a read operation.
BP0, BP1, BP2 (bits 2, 3, 4)
Block protect BP0, BP1, and BP2 are status register bits that can be rewritten, and the memory space to be protected
can be set depending on these bits. For the setting conditions, refer to "Table 4 Protect level setting conditions".
Table 4 Protect Level Setting Conditions
Protect Level
Status Register Bits
Protected Area
BP2 BP1 BP0
0 (Whole area unprotected) 0 0 0 None
1 (1/16 protected) 0 0 1 F0000h to FFFFFh
2 (1/8 protected) 0 1 0 E0000h to FFFFFh
3 (1/4 protected) 0 1 1 C0000h to FFFFFh
4 (1/2 protected) 1 0 0 80000h to FFFFFh
5 (Whole area protected) 1 0 1 00000h to FFFFFh
5 (Whole area protected) 1 1 0 00000h to FFFFFh
5 (Whole area protected) 1 1 1 00000h to FFFFFh
* Chip erase is enabled only when the protect level is 0.
SRWP (bit 7)
Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten.
When SRWP is "1" and the logic level of the WP
pin is low, the status register write command is ignored, and status
registers BP0, BP1, BP2, and SRWP are protected. When the logic level of the WP
pin is high, the status registers
are not protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 5 SRWP setting
conditions".
Table 5 SRWP Setting Conditions
WP
Pin SRWP Status Register Protect State
0
0 Unprotected
1 Protected
1
0 Unprotected
1 Unprotected
Bits 5 and 6 are reserved bits, and have no significance.
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LE25W81QES00-AH-1

Mfr. #:
Buy LE25W81QES00-AH-1
Manufacturer:
ON Semiconductor
Description:
NOR Flash S-FLASH MEMORY(8M)
Lifecycle:
New from this manufacturer.
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