OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

932S401EGLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
10
Integrated
Circuit
Systems, Inc.
ICS932S401
0921G—08/24/09
Test Load
CL=5pF
Rs
Zo
ICS932S401
SEPP Output Buffer
(Single Ended
Push Pull)
Rs
Zo
Rs
Zo
SEPP Output Buffer
(Single Ended
Push Pull)
CL=5pF
CL=5pF
The singled-ended outputs of the ICS 932S401E default to a drive strength of 2
loads. The REF clocks can be turned down to 1-load strength via the SMBus.
Suggested termination resistors are as follows for transmission lines with Zo =
50 ohms:
Driving 1 load, Rs = 33 ohms
Driving 2 loads, Rs = 7.5 ohms
Single-ended outputs at 1-load strength (REF clock only) Driving 1 load, Rs = 22 ohms
Single-ended outputs at 2-load strength (Power up default
for all single-ended outputs)
Single-ended Output Terminations
11
Integrated
Circuit
Systems, Inc.
ICS932S401
0921G—08/24/09
General SMBus serial interface information for the ICS932S401
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will
acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will
acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends
Byte N + X -1
• ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byte
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
12
Integrated
Circuit
Systems, Inc.
ICS932S401
0921G—08/24/09
SMBus Table: SRC Output Enable Register
Pin # Name Control Function Type 0 1 PWD
Bit 7
SRCCLK7 Enable Output Enable RW Disable-Hi-Z Enable 1
Bit 6
SRCCLK6 Enable Output Enable RW Disable-Hi-Z Enable 1
Bit 5
SRCCLK5 Enable Output Enable RW Disable-Hi-Z Enable 1
Bit 4
SRCCLK4 Enable Output Enable RW Disable-Hi-Z Enable 1
Bit 3
SRCCLK3 Enable Output Enable RW Disable-Hi-Z Enable 1
Bit 2
SRCCLK2 Enable Output Enable RW Disable-Hi-Z Enable 1
Bit 1
SRCCLK1 Enable Output Enable RW Disable-Hi-Z Enable 1
Bit 0
SRCCLK0 Enable Output Enable RW Disable-Hi-Z Enable 1
SMBus Table: CPU, REF and 48 MHz Output Enable Register
Pin # Name Control Function Type 0 1 PWD
Bit 7
REF1 Enable Output Enable RW Disable-Low Enable 1
Bit 6
REF0 Enable Output Enable RW Disable-Low Enable 1
Bit 5
CPUCLK3 Output Enable RW Disable-Hi-Z Enable 1
Bit 4
CPUCLK2 Output Enable RW Disable-Hi-Z Enable 1
Bit 3
0
Bit 2
CPUCLK1 Output Enable RW Disable-Hi-Z Enable 1
Bit 1
CPUCLK0 Output Enable RW Disable-Hi-Z Enable 1
Bit 0
Spread Spectrum Enable Spread Off/On RW Spread Off Spread On 0
SMBus Table: PCI and PCICLK_F Output Enable Register
Pin # Name Control Function Type 0 1 PWD
Bit 7
PCICLK3 Output Enable RW Disable-Low Enable 1
Bit 6
PCICLK2 Output Enable RW Disable-Low Enable 1
Bit 5
PCICLK1 Output Enable RW Disable-Low Enable 1
Bit 4
PCICLK0 Output Enable RW Disable-Low Enable 1
Bit 3
PCICLK_F2 Enable Output Enable RW Disable-Low Enable 1
Bit 2
PCICLK_F1 Enable Output Enable RW Disable-Low Enable 1
Bit 1
PCICLK_F0 Enable Output Enable RW Disable-Low Enable 1
Bit 0
48MHz Enable Output Enable RW Disable-Low Enable 1
SMBus Table: PCICLK_F and SRC Stop Control Register
Pin # Name Control Function Type 0 1 PWD
Bit 7
PCICLK_F2 Stop En RW Free-Running Stoppable 1
Bit 6
PCICLK_F1 Stop En RW Free-Running Stoppable 1
Bit 5
PCICLK_F0 Stop En RW Free-Running Stoppable 1
Bit 4
SRCCLK4 Stop En RW Free-Running Stoppable 1
Bit 3
SRCCLK3 Stop En RW Free-Running Stoppable 1
Bit 2
SRCCLK2 Stop En RW Free-Running Stoppable 1
Bit 1
SRCCLK1 Stop En RW Free-Running Stoppable 1
Bit 0
SRCCLK0 Stop En RW Free-Running Stoppable 1
42,43
6
5
45,46
23,24
21,22
36,37
16,17
Byte 1
55
18,19
54
39,40
Byte 0
NA
NA
26,27
NA
Free-Running Control, Default: not
affected by PCI/SRC_STOP
(Byte 6, bit 3)
16,17
18,19
21,22
23,24
4
CPU, SRC,
PCI
Byte 2
10
26,27
9
RESERVED
Byte 3
10
9
11
13
3
11
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

932S401EGLFT

Mfr. #:
Buy 932S401EGLFT
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner SERVER MAIN CLOCK - CK410B
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet