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932S401EGLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
4
Integrated
Circuit
Systems, Inc.
ICS932S401
0921G—08/24/09
ICS932S401 is a main clock synthesizer for CK410-generation Intel server platforms. ICS932S401 is driven with a 14.318MHz
crystal. It generates CPU outputs up to 400MHz and PCI-Express clocks at 100 or 200 MHz. The 48 MHz USB clock is an exact
48.000 MHz clock. The ICS932S401 generates all clocks with less the +/- 300 ppm error.
General Description
Block Diagram
Power Groups
CPU PLL
PCICLK(3:0), PCICLK_F(2:0)
CONTROL
LOGIC
XTAL
OSC.
CPUCLK(2:0)
FIXED PLL
48MHz
DIVIDER
DIVIDERS
REF(1:0)
SRCCLK(4:0)
S DATA
SCLK
X1
X2
IREF
FS(C:A)
VTT_PWRGD#/PD
SRC/PCI
PLL
DIVIDERS
TEST_SEL
VDD GND
53 50 Xtal, Ref
1,8 2,7 PCICLK outputs
15,25,28 20 SRCCLK outputs
35 34 Master clock, CPU Analog
12 14 48MHz, PLL_48
47,44,38 41 CPUCLK clocks
Description
Pin Number
5
Integrated
Circuit
Systems, Inc.
ICS932S401
0921G—08/24/09
Absolute Max
Symbol Parameter Min Max Units
VDD_A 3.3V Core Supply Voltage
V
DD
+ 0.5V
V
VDD_In 3.3V Logic Input Supply Voltage GND - 0.5
V
DD
+ 0.5V
V
Ts Storage Temperature -65 150
°
C
Tambient Ambient O
p
eratin
g
Tem
p
070°C
Tcase Case Tem
p
erature 115 °C
ESD prot
Input ESD protection
human bod
y
model
2000 V
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage V
IH
3.3 V +/-5% 2 V
DD
+ 0.3 V
Input Low Voltage V
IL
3.3 V +/-5% V
SS
- 0.3 0.8 V
Input High Current I
IH
V
IN
= V
D
D
-5 5 uA
I
IL1
V
IN
= 0 V; Inputs with no pull-
up resistors
-5 uA
I
IL2
V
IN
= 0 V; Inputs with pull-up
resistors
-200 uA
Low Threshold Input High
Voltage
V
IH_FS
3.3 V +/-5% 0.7 V
DD
+ 0.3 V
Low Threshold Input Low
Voltage
V
IL_FS
3.3 V +/-5% V
SS
- 0.3 0.35 V
Operating Supply Current I
DD3.3OP
3.3 V +/-5%, Full Load 270 350 mA
all diff pairs driven
60
90 mA
all differential pairs tri-stated
9
15 mA
Input Frequency
3
F
i
V
DD
= 3.3 V 14.31818 MHz 3
Pin Inductance
1
L
p
in
7nH1
C
IN
Logic Inputs 5 pF 1
C
OUT
Output pin capacitance 6 pF 1
C
INX
X1 & X2 pins 5 pF 1
Clk Stabilization
1,2
T
STAB
From V
DD
Power-Up or de-
assertion of PD# to 1st clock
1.8 ms 1,2
Modulation Frequency Triangular Modulation 30 33 kHz 1
Tdrive_PD#
CPU output enable after
PD# de-assertion
300 us 1
Tfall_Pd# PD# fall time of 5 ns 1
Trise_Pd# PD# rise time of 5 ns 2
SMBus Voltage V
IMAX
Max. Voltage on SCLK/SDAT 5.5 V 1
Low-level Output Voltage V
OLSMBUS
@ I
PULLUP
0.4 V 1
C
urrent sinking at V
OL
= 0.4
V
I
PULLUP
4mA1
SCLK/SDATA
Clock/Data Rise Time
T
RI2C
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA
Clock/Data Fall Time
T
FI2C
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
See timing diagrams for timing requirements.
3
Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm accuracy on
PLL outputs.
Input Low Current
Powerdown Current I
DD3.3PD
Input Capacitance
1
6
Integrated
Circuit
Systems, Inc.
ICS932S401
0921G—08/24/09
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33.2
Ω
, R
P
=49.9
Ω, Ι
REF
= 475Ω
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Current Source Output
Im
p
edance
Zo
V
O
= V
x
3000
Ω
1
Voltage High VHigh 660 775 850 1
Voltage Low VLow -150 70 150 1
Max Volta
g
eVovs 1150 1
Min Volta
g
e Vuds -300 1
Crossin
g
Volta
g
e
(
abs
)
Vcross
(
abs
)
250 355 550 mV 1
Crossing Voltage (var) d-Vcross Variation of crossing over all edges 90 140 mV 1
Lon
g
Accurac
y
pp
m see T
p
eriod min-max values -300 0 300
pp
m 1,2
400MHz nominal 2.4993 2.5008 ns 2
400MHz s
p
read 2.4993 2.5133 ns 2
333.33MHz nominal 2.9991 3.0009 ns 2
333.33MHz s
p
read 2.9991 3.016 ns 2
266.66MHz nominal 3.7489 3.7511 ns 2
266.66MHz s
p
read 3.7489 3.77 ns 2
200MHz nominal 4.9985 5.0015 ns 2
200MHz s
p
read 4.9985 5.0266 ns 2
166.66MHz nominal 5.9982 6.0018 ns 2
166.66MHz s
p
read 5.9982 6.0320 ns 2
133.33MHz nominal 7.4978 7.5023 ns 2
133.33MHz s
p
read 7.4978 7.5400 ns 2
100.00MHz nominal 9.9970 10.0030 ns 2
100.00MHz s
p
read 9.9970 10.0533 ns 2
400MHz nominal/s
p
read 2.4143 ns 1,2
333.33MHz nominal/s
p
read 2.9141 ns 1,2
266.66MHz nominal/s
p
read 3.6639 ns 1,2
200MHz nominal/s
p
read 4.8735 ns 1,2
166.66MHz nominal/s
p
read 5.8732 ns 1,2
133.33MHz nominal/s
p
read 7.4128 ns 1,2
100.00MHz nominal/s
p
read 9.8720 ns 1,2
Rise Time
t
r
V
OL
= 0.175V, V
OH
= 0.525V
175 240 700 ps 1
Fall Time
t
f
V
OH
= 0.525V V
OL
= 0.175V
175 359 700 ps 1
Rise Time Variation
d-t
r
49 125 ps 1
Fall Time Variation
d-t
f
59 125 ps 1
Duty Cycle
d
t3
Measurement from differential
wavefrom
45 49 55 % 1
Skew
t
sk3
CPU (3:0) V
T
= 50%
33 50 ps 1
Jitter, Cycle to cycle
t
jcyc-cyc
Measurement from differential
wavefrom
38 50 ps 1
1
Guaranteed b
y
desi
g
n, not 100% tested in
p
roduction.
2
All Lon
g
Term Accurac
y
and Clock Period s
p
ecifications are
g
uaranteed assumin
g
that REFout is at 14.31818MHz
T
absmin
Absolute min period
Statistical measurement on single
ended signal using oscilloscope
math function.
mV
Measurement on single ended
signal using absolute value.
mV
Average period Tperiod
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

932S401EGLFT

Mfr. #:
Buy 932S401EGLFT
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner SERVER MAIN CLOCK - CK410B
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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