16
Integrated
Circuit
Systems, Inc.
ICS932S401
0921G—08/24/09
SMBus Table: SRC Frequency Control Register
Pin # Name Control Function Type 0 1 PWD
Bit 7
SRC N Div8 N Divider Prog bit 8 RW X
Bit 6
SRC N Div9 N Divider Prog bit 9 RW X
Bit 5
SRC M Div5 RW X
Bit 4
SRC M Div4 RW X
Bit 3
SRC M Div3 RW X
Bit 2
SRC M Div2 RW X
Bit 1
SRC M Div1 RW X
Bit 0
SRC M Div0 RW X
SMBus Table: SRC Frequency Control Register
Pin # Name Control Function Type 0 1 PWD
Bit 7
SRC N Div7 RW X
Bit 6
SRC N Div6 RW X
Bit 5
SRC N Div5 RW X
Bit 4
SRC N Div4 RW X
Bit 3
SRC N Div3 RW X
Bit 2
SRC N Div2 RW X
Bit 1
SRC N Div1 RW X
Bit 0
SRC N Div0 RW X
SMBus Table: SRC Spread Spectrum Control Register
Pin # Name Control Function Type 0 1 PWD
Bit 7
SRC SSP7 RW X
Bit 6
SRC SSP6 RW X
Bit 5
SRC SSP5 RW X
Bit 4
SRC SSP4 RW X
Bit 3
SRC SSP3 RW X
Bit 2
SRC SSP2 RW X
Bit 1
SRC SSP1 RW X
Bit 0
SRC SSP0 RW X
SMBus Table: SRC Spread Spectrum Control Register
Pin # Name Control Function Type 0 1 PWD
Bit 7
Reserved Reserved R - - 0
Bit 6
SRC SSP14 RW X
Bit 5
SRC SSP13 RW X
Bit 4
SRC SSP12 RW X
Bit 3
SRC SSP11 RW X
Bit 2
SRC SSP10 RW X
Bit 1
SRC SSP9 RW X
Bit 0
SRC SSP8 RW X
Byte 18
Byte 15
Byte 16
-
-
-
-
-
-
These Spread Spectrum bits in
Byte 17 and 18 will program
the spread pecentage of SRC
Spread Spectrum Programming b(7:0)
The decimal representation of
M and N Divider in Byte 15 and
16 will configure the SRC VCO
frequency. Default at power
up = latch-in or Byte 0 Rom
table. VCO Frequency =
14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
M Divider Programming bits
These Spread Spectrum bits in
Byte 17 and 18 will program
the spread pecentage of SRC
-
-
-
-
-
-
-
-
Spread Spectrum Programming
b(14:8)
-
-
-
-
-
-
-
-
-
Byte 17
-
N Divider Programming b(7:0)
The decimal representation of
M and N Divider in Byte 15 and
16 will configure the SRC VCO
frequency. Default at power
up = latch-in or Byte 0 Rom
table. VCO Frequency =
14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
-
-
-
-
-
-
-
-
17
Integrated
Circuit
Systems, Inc.
ICS932S401
0921G—08/24/09
SMBus Table: CPU Programmable Output Divider Register
Pin # Name Control Function Type 0 1 PWD
Bit 7
CPUDiv3 RW X
Bit 6
CPUDiv2 RW X
Bit 5
CPUDiv1 RW X
Bit 4
CPUDiv0 RW X
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
SMBus Table: SRC and PCI Programmable Output Divider Register
Pin # Name Control Function Type 0 1 PWD
Bit 7
PCIDiv3 RW X
Bit 6
PCIDiv2 RW X
Bit 5
PCIDiv1 RW X
Bit 4
PCIDiv0 RW X
Bit 3
SRC_Div3 RW X
Bit 2
SRC_Div2 RW X
Bit 1
SRC_Div1 RW X
Bit 0
SRC_Div0 RW X
SMBusTable: Test Byte Register
Test Type PWD
Bit 7
RW 0
Bit 6
RW 0
Bit 5
RW 0
Bit 4
RW 0
Bit 3
RW 0
Bit 2
RW 0
Bit 1
RW 0
Bit 0
RW 0
Note: Do NOT write to Bit 21. Erratic device operation will result!
Byte 19
Byte 20
-
-
-
See CPU, SRC and PCI
Divider Ratios Table
See CPU, SRC and PCI
Divider Ratios Table
RESERVED
RESERVED
RESERVED
RESERVED
CPU Divider Ratio Programming Bits
ICS ONLY TEST Reserved
ICS ONLY TEST Reserved
ICS ONLY TEST Reserved
ICS ONLY TEST Reserved
ICS ONLY TEST Reserved
ICS ONLY TEST Reserved
ICS ONLY TEST Reserved
Test Function Test Result
` ICS ONLY TEST Reserved
Byte 21
-
SRC_ Divider Ratio Programming Bits
-
-
-
-
PCI Divider Ratio Programming Bits
-
-
-
-
See CPU, SRC and PCI
Divider Ratios Table
18
Integrated
Circuit
Systems, Inc.
ICS932S401
0921G—08/24/09
REF Drive Strength Functionality
Byte6,
bit 4
Byte 10,
bit 1
Byte 10,
bit 0 REF1 REF0
0X X1x1x
10 01x1x
10 11x2x
11 02x1x
11 12x2x
CPU, SRC and PCI Divider Ratios
Div(3:0) Divider
00000 2
10001 3
20010 5
30011 15
40100 4
50101 6
60110 10
70111 30
81000 8
91001 12
10 1010 20
11 1011 60
12 1100 16
13 1101 24
14 1110 40
15 1111 120

932S401EGLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner SERVER MAIN CLOCK - CK410B
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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