NCD5703A, NCD5703B, NCD5703C
www.onsemi.com
14
Gate Voltage Range
The negative drive voltage for gate (with respect to GND,
or Emitter of the IGBT) is a robust way to ensure that the gate
voltage does not rise above the threshold voltage due to the
Miller effect. In systems where the negative power supply is
available, the VEE option offered by NCD5703B allows not
only a robust operation, but also a higher drive current for
turn−off transition. Adequate bypassing between VEE pin
and GND pin is essential if this option is used.
The V
CC
range for the NCD5703 is quite wide and allows
the user the flexibility to optimize the performance or use
available power supplies for convenience.
Under Voltage Lock Out (UVLO)
This feature ensures reliable switching of the IGBT
connected to the driver output. At the start of the driver’s
operation when V
CC
is applied to the driver, the output
remains turned−off. This is regardless of the signals on V
IN
until the V
CC
reaches the UVLO Output Enabled
(V
UVLO−OUT−ON
) level. After the V
CC
rises above the
V
UVLO−OUT−ON
level, the driver is in normal operation. The
state of the output is controlled by signal at V
IN
.
If the V
CC
falls below the UVLO Output Disabled
(V
UVLO−OUT−OFF
) level during the normal operation of the
driver, the Fault output is activated and the output is shut−down
(after a delay) and remains in this state. The driver output
does not start to react to the input signal on V
IN
until the V
CC
rises above the V
UVLO−OUT−ON
again. The waveform
showing the UVLO behavior of the driver is in Figure 21.
In an IGBT drive circuit, the drive voltage level is
important for drive circuit optimization. If V
UVLO−OUT−OFF
is too low, it will lead to IGBT being driven with insufficient
gate voltage. A quick review of IGBT characteristics can
reveal that driving IGBT with low voltage (in 10−12 V
range) can lead to a significant increase in conduction loss.
So, it is prudent to guarantee V
UVLO−OUT−OFF
at a
reasonable level (above 12 V), so that the IGBT is not forced
to operate at a non−optimum gate voltage. On the other hand,
having a very high drive voltage ends up increasing
switching losses without much corresponding reduction in
conduction loss. So, the V
UVLO−OUT−ON
value should not
be too high (generally, well below 15 V). These conditions
lead to a tight band for UVLO enable and disable voltages,
while guaranteeing a minimum hysteresis between the two
values to prevent hiccup mode operation. The NCD5703
meets these tight requirements and ensures smooth IGBT
operation. It ensures that a 15 V supply with ±8% tolerance
will work without degrading IGBT performance, and
guarantees that a fault will be reported and the IGBT will be
turned off when the supply voltage drops below 12.2 V.
A UVLO event (V
CC
voltage going below V
UVLO−OUT−OFF
)
also triggers activation of FLT
output after a delay of t
d3−FLT
.
This indicates to the controller that the driver has
encountered an issue and corrective action needs to be taken.
However, a nominal delay t
d1−OUT
= 12 ms is introduced
between the initiation of the FLT
output and actual turning
off of the output. This delay provides adequate time for the
controller to initiate a more orderly/sequenced shutdown. In
case the controller fails to do so, the driver output shutdown
ensures IGBT protection after t
d1−OUT
.
Figure 21. UVLO Function and Limits
Timing Delays and Impact on System Performance
The gate driver is ideally required to transmit the input
signal pulse to its output without any delay or distortion. In
the context of a high−power system where IGBTs are
typically used, relatively low switching frequency (in tens of
kHz) means that the delay through the driver itself may not
be as significant, but the matching of the delay between
different drivers in the same system as well as between
different edges has significant importance. With reference to
Figure 22(a), two input waveforms are shown. They are
typical complementary inputs for high−side (HS) and
low−side (LS) of a half−bridge switching configuration. The
dead−time between the two inputs ensures safe transition
between the two switches. However, once these inputs are
through the driver, there is potential for the actual gate
voltages for HS and LS to be quite different from the
intended input waveforms as shown in Figure 22(a). The end
result could be a loss of the intended dead−time and/or
pulse−width distortion. The pulse−width distortion can
create an imbalance that needs to be corrected, while the loss
of dead−time can eventually lead to cross−conduction of the
switches and additional power losses or damage to the
system.
The NCD5703 driver is designed to address these timing
challenges by providing a very low pulse−width distortion
and excellent delay matching. As an example, the delay
matching is guaranteed to t
DISTORT2
= ±25 ns while many
of competing driver solutions can be >250 ns.
