NCP51705
www.onsemi.com
15
cross−conduction prevention between a high−side and
low−side switch used in a half or full−bridge configuration.
The schematic diagram shown in Figure 33 illustrates a
circuit example how to utilize the XEN signals for fault
detection and cross−conduction prevention. As can be seen
in this implementation, the functions are independent and it
is up to the designer to decide whether any one or both
functions are needed to be implemented in the system.
FLT_HS
FLT_LS
PWM_HS
PWM_LS
XEN_HS
XEN_LS
IN+_HS
IN+_LS
FAULT
DETECTION
ANTI CROSS−
CONDUCTION
Figure 33. Examples of XEN signal usage
If XEN_HS transitions from LOW to HIGH while
PWM_HS is HIGH, the PWM pulse width had been
terminated early by one of the protection functions of the
NCP51705. The protection function are; any of the Under
Voltage Lock−Out (UVLO) protections, Thermal Shut
Down (TSD), and Desaturation Detection (DESAT). As
Figure 33 indicates a FAULT signal can be generated by a
simple AND connection of the PWM input signal and the
corresponding XEN output.
In case of cross−conduction prevention, the XEN signal of
one driver is used to enable the operation of the other driver
as depicted in a simplified manner in Figure 33. The
isolation for the high side driver is not shown in the
simplified schematic of Figure 33 but the operation of the
system can be easily followed. While the high−side driver is
ON, XEN_HS is LOW preventing any gate drive to be
applied to the low−side driver. Once the high−side driver
turns OFF its XEN_HS signal transitions to HIGH and the
PWM_LS signal can pass through to the low−side driver. An
identical sequence exists to ensure that the high−side driver
cannot be turned ON until the low−side driver is OFF.
Signal Ground (SGND) and Power Ground (PGND)
Signal ground connection (SGND) is the GND for all
control logic biased from the 5 V rail (V5V). Internally, the
SGND and PGND pins are tied together by two anti−parallel
diodes to limit ground bounce difference due to bond wire
inductances during the switching actions of the high−current
gate drive circuits. It is recommended to connect the SGND
and PGND pins together with a short, low−impedance trace
on the PCB.
PGND is the reference potential (0 V) for the high−current
gate−drive circuit. Two bypass capacitors should be
connected between the VDD pin and the PGND pin. One is
the V
DD
energy storage capacitor, which provides bias
power during startup until the bootstrap power supply comes
up. The value of the energy storage capacitor is a strong
function of the gate charge requirement of the SiC
MOSFET. It is recommended to use a minimum of 1 mF to
ensure proper operation but the value is primarily dictated
by the biasing scheme and startup time of the system. The
second capacitor shall be a good−quality ceramic bypass
capacitor, located as close as possible to the PGND and
VDD pins to filter the high peak currents of the gate driver
source circuit. A ceramic bypass capacitor in the range of
10 nF to 100 nF is recommended.
Similarly, two bypass capacitors should be connected
between the VEE pin and the PGND pin. One is the V
EE
energy storage capacitor, which smoothes the ripple voltage
seen at output of the internal charge pump power stage. It is
recommended to use a minimum of 470 nF to ensure
accurate DC regulation. The second capacitor shall be a
good−quality ceramic bypass capacitor, located as close as
possible to the PGND and VEE pins to filter the high peak
currents of the gate driver sink circuit. A ceramic bypass
capacitor in the range of 10 nF to 100 nF is recommended.
Note that the exposed metal pad beneath the IC is
thermally conductive but electrically not always connected
to GND potential. Do not connect this pad to SGND or
PGND.
Programmable VEE Voltage (VEESET)
V
EE
is regulated to the voltage set at V
CH
which is
determined by the internal low dropout regulator (LDO)
voltage, programmable by the VEESET pin. The
NCP51705 offers several convenient pin strapping options
for VEESET. If VEESET is left floating (a 100 pF bypass
capacitor from VEESET to SGND is recommended), then
V
EE
is set to regulate at −3 V. For a −5 V V
EE
voltage, the
VEESET pin should be connected directly to V5V (pin 23).
If VEESET is connected to any voltage between 9 V and
V
DD
, then V
EE
is clamped and set to regulate at the
minimum charge pump voltage of −8 V. The charge pump
starts when V
DD
> 7.5 V. Additionally, the V
EE
voltage rail
includes an internally fixed under−voltage lockout (UVLO)
set to 80% of the programmed V
EE
value. Since V
DD
and
V
EE
are each monitored by independent UVLO circuits, the
NCP51705 is smart enough to realize when both voltage
rails are within limits deemed safe for switching a given SiC
MOSFET.
Some SiC MOSFETs can operate between 0 V and VDD.
For these applications, 0 V<OUT<V
DD
switching can be
achieved by disabling the charge pump entirely. When
VEESET is connected to SGND and VEE is connected to
PGND, the charge pump is disabled. With the charge pump
disabled and V
EE
tied directly to PGND, the output switches
between 0 V<OUT<V
DD
. During this mode of operation the
internal V
EE
UVLO function is also disabled accordingly.
