NCP51705
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19
Applications Information – HighSide Gate Drive Example
Many highvoltage switching applications use power
topologies that include highside, lowside gate drive
schemes. Some well known examples include converter
topologies such as: LLC, halfbridge and fullbidge. The
NCP51705 can be applied in halfbridge (or fullbridge)
power topologies such as the one shown in Figure 40.
Highvoltage applications tend to prefer isolated drivers for
both, the highside and lowside gate drive. This implies the
need for two digital isolators. In addition to providing
electrical safety and galvanic isolation, the digital isolator
assigned to the highside gate driver, serves the dual purpose
of level shifting the IN+ PWM input signal. Since the
lowside drive is ground referenced, the digital isolator
dedicated to the lowside gate drive is not level shifted and
therefore only serves the purpose of electrical safety and
galvanic isolation. In this simplified example, IN+
(noninverting PWM logic) and IN (active enable) are the
only two signals sourced from the digital controller and
XEN is read back from the NCP51705. XEN can be used as
the timing information basis for developing gate drive
timing, cross conduction prevention, deadtime adjustment
and fault detection. The V5V from the NCP51705 can be
used to power the secondary side of each digital isolator as
shown Figure 40.
Digital Controller
Isolation
Boundary
ENABLE
PWM_HS
XEN_HS
PWM_LS
XEN_LS
FAULT _HS
FAULT _LS
Digital
Isolators
ISOLATOR BIAS
ISOLATOR BIAS
CONTROLLER BIAS (3.3 V or 5 V)
20 V BIAS (isolated)
20 V BIAS (isolated)
Figure 40. NCP51705 HalfBridge Gate Drive
NCP51705
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PCB Guideline
NCP51705
(Top View )
1
2
3
4
7
8
9
10
PGND
PGND
IN+
IN
XEN
VCH
C+
PGND
VEE
OUTSNK
OUTSRC
UVSET
V5V
VDD
11
12
5
6
18
17
16
15
14
13
24
23
22
21
20
19
OUTSRC
PGND
OUTSNK
VEE
VDD
SGND
C
SVDD
VEESET
DESAT
Figure 41. Recommend PCB drawing
First of all, to optimize operation of SiC gate driving
should be minimize influence of the parasitic inductance and
capacitance on the layout. The following should be
considered before beginning a PCB layout using the
NCP51705.
The SiC driver should be locate as close as possible to
the SiC MOSFET.
VDD, SVDD, V5V, Charge Pump and VEE capacitor
should be locate as close as possible to the device.
When the VEESET = GND, the VEE should be as
close as possible to the PGND trace.
Driver input and DESAT should not going close to the
high dV/dT traces. It can cause abnormal operation by
significant noise.
If the device operates in the high temperature condition,
use thermal via distribution from exposed pad to the
other layer to make the thermal resistance as low as
possible. In this case, do not connect the thermal pad to
SGND or PGND.
Use wide traces for OUTSRC, OUTSNK and VEE
related with main gate driving path.
NCP51705
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21
PACKAGE DIMENSIONS
QFN24, 4x4, 0.5P
CASE 485L
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
SEATING
PLANE
D
B
0.15 C
A
A3
A
E
PIN 1
REFEENCE
2X
0.15 C
2X
0.08 C
0.10 C
C
DIM MIN MAX
MILLIMETERS
A 0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b 0.20 0.30
D 4.00 BSC
D2 2.70 2.90
E 4.00 BSC
E2 2.70 2.90
e 0.50 BSC
L 0.30 0.50
24X
L
D2
b
1
7
13
19
e/2
E2
e
24
0.10 B
0.05
AC
C
L1
DETAIL A
L
ALTERNATE
CONSTRUCTIONS
L
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE TERMINAL
CONSTRUCTIONS
A1
A3
TOP VIEW
SIDE VIEW
DETAIL B
BOTTOM VIEW
DETAIL A
SOLDERING FOOTPRINT
DIMENSIONS: MILLIMETERS
2.90
4.30
4.30
0.50
0.55
0.32
24X
24X
PITCH
1
2.90
RECOMMENDED
NOTE 4
A1
24X
NOTE 3
L1 0.05 0.15
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NCP51705MNTXG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Gate Drivers SIC MOSFET DRIVER
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New from this manufacturer.
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