DS18B20-PAR
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The master device can check the alarm flag status of all DS DS18B20-PARs on the bus by issuing an
Alarm Search [ECh] command. Any DS18B20-PARs with a set alarm flag will respond to the command,
so the master can determine exactly which DS18B20-PARs have experienced an alarm condition. If an
alarm condition exists and the T
H
or T
L
settings have changed, another temperature conversion should be
done to validate the alarm condition.
64-BIT LASERED ROM CODE
Each DS18B20-PAR contains a unique 64–bit code (see Figure 5) stored in ROM. The least significant 8
bits of the ROM code contain the DS18B20-PAR’s 1–wire family code: 28h. The next 48 bits contain a
unique serial number. The most significant 8 bits contain a cyclic redundancy check (CRC) byte that is
calculated from the first 56 bits of the ROM code. A detailed explanation of the CRC bits is provided in
the CRC GENERATION section. The 64–bit ROM code and associated ROM function control logic
allow the DS18B20-PAR to operate as a 1–wire device using the protocol detailed in the 1-WIRE BUS
SYSTEM section of this datasheet.
64-BIT LASERED ROM CODE Figure 5
8-BIT CRC 48-BIT SERIAL NUMBER 8-BIT FAMILY CODE (28h)
MEMORY
The DS18B20-PAR’s memory is organized as shown in Figure 6. The memory consists of an SRAM
scratchpad with nonvolatile EEPROM storage for the high and low alarm trigger registers (T
H
and T
L
)
and configuration register. Note that if the DS18B20-PAR alarm function is not used, the T
H
and T
L
registers can serve as general-purpose memory. All memory commands are described in detail in the
DS18B20-PAR FUNCTION COMMANDS section.
Byte 0 and byte 1 of the scratchpad contain the LSB and the MSB of the temperature register,
respectively. These bytes are read-only. Bytes 2 and 3 provide access to T
H
and T
L
registers. Byte 4
contains the configuration register data, which is explained in detail in the CONFIGURATION
REGISTER section of this datasheet. Bytes 5, 6 and 7 are reserved for internal use by the device and
cannot be overwritten.
Byte 8 of the scratchpad is read-only and contains the cyclic redundancy check (CRC) code for bytes 0
through 7 of the scratchpad. The DS18B20-PAR generates this CRC using the method described in the
CRC GENERATION section.
Data is written to bytes 2, 3, and 4 of the scratchpad using the Write Scratchpad [4Eh] command, and the
data must be transmitted to the DS18B20-PAR starting with the least significant bit of byte 2. To verify
data integrity, the scratchpad can be read (using the Read Scratchpad [BEh] command) after the data is
written. When reading the scratchpad, data is transferred over the 1-Wire bus starting with the least
significant bit of byte 0. To transfer the T
H
, T
L
and configuration data from the scratchpad to EEPROM,
the master must issue the Copy Scratchpad [48h] command.
Data in the EEPROM registers is retained when the device is powered down; at power-up the EEPROM
data is reloaded into the corresponding scratchpad locations. Data can also be reloaded from EEPROM
to the scratchpad at any time using the Recall E
2
[B8h] command. The master can issue “read time slots”
(see the 1-WIRE BUS SYSTEM section) following the Recall E
2
command and the DS18B20-PAR will
indicate the status of the recall by transmitting 0 while the recall is in progress and 1 when the recall is
done.
MSB MSB LSB LSB LSBMSB
