DS18B20+PAR Datasheet DS18B20+PAR | P7-P9

DS18B20-PAR

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and then compare this value to either the ROM code CRC (for ROM reads) or to the scratchpad CRC (for

scratchpad reads). If the calculated CRC matches the read CRC, the data has been received error free. The

comparison of CRC values and the decision to continue with an operation are determined entirely by the

bus master. There is no circuitry inside the DS18B20-PAR that prevents a command sequence from

proceeding if the DS18B20-PAR CRC (ROM or scratchpad) does not match the value generated by the

bus master.

The equivalent polynomial function of the CRC (ROM or scratchpad) is: CRC = X

+ X

+ 1

The bus master can re-calculate the CRC and compare it to the CRC values from the DS18B20-PAR

using the polynomial generator shown in Figure 8. This circuit consists of a shift register and XOR gates,

and the shift register bits are initialized to 0. Starting with the least significant bit of the ROM code or the

least significant bit of byte 0 in the scratchpad, one bit at a time should shifted into the shift register.

After shifting in the 56

bit from the ROM or the most significant bit of byte 7 from the scratchpad, the

polynomial generator will contain the re-calculated CRC. Next, the 8-bit ROM code or scratchpad CRC

from the DS18B20-PAR must be shifted into the circuit. At this point, if the re-calculated CRC was

correct, the shift register will contain all 0s. Additional information about the Dallas 1-Wire cyclic

redundancy check is available in Application Note 27 entitled “Understanding and Using Cyclic

Redundancy Checks with Dallas Semiconductor Touch Memory Products.”

CRC GENERATOR Figure 8

1-WIRE BUS SYSTEM

The 1-Wire bus system uses a single bus master to control one or more slave devices. The DS18B20-

PAR is always a slave. When there is only one slave on the bus, the system is referred to as a “single-

drop” system; the system is “multi-drop” if there are multiple slaves on the bus.

All data and commands are transmitted least significant bit first over the 1-Wire bus.

The following discussion of the 1-Wire bus system is broken down into three topics: hardware

configuration, transaction sequence, and 1-Wire signaling (signal types and timing).

HARDWARE CONFIGURATION

The 1-Wire bus has by definition only a single data line. Each device (master or slave) interfaces to the

data line via an open drain or 3–state port. This allows each device to “release” the data line when the

device is not transmitting data so the bus is available for use by another device. The 1-Wire port of the

DS18B20-PAR (the DQ pin) is open drain with an internal circuit equivalent to that shown in Figure 9.

The 1-Wire bus requires an external pullup resistor of approximately 5 kΩ; thus, the idle state for the 1-

Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle

state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1-Wire

bus is in the inactive (high) state during the recovery period. If the bus is held low for more than 480 μs,

all components on the bus will be reset. In addition, to assure that the DS18B20-PAR has sufficient

supply current during temperature conversions, it is necessary to provide a strong pullup (such as a

MOSFET) on the 1-Wire bus whenever temperature conversions or EEPROM writes are taking place (as

described in the PARASITE POWER section).

(MSB) (LSB)

XOR XOR

XOR

INPUT

DS18B20-PAR

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HARDWARE CONFIGURATION Figure 9

TRANSACTION SEQUENCE

The transaction sequence for accessing the DS18B20-PAR is as follows:

Step 1. Initialization

Step 2. ROM Command (followed by any required data exchange)

Step 3. DS18B20-PAR Function Command (followed by any required data exchange)

It is very important to follow this sequence every time the DS18B20-PAR is accessed, as the DS18B20-

PAR will not respond if any steps in the sequence are missing or out of order. Exceptions to this rule are

the Search ROM [F0h] and Alarm Search [ECh] commands. After issuing either of these ROM

commands, the master must return to Step 1 in the sequence.

INITIALIZATION

All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence

consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the

slave(s). The presence pulse lets the bus master know that slave devices (such as the DS18B20-PAR) are

on the bus and are ready to operate. Timing for the reset and presence pulses is detailed in the

1-WIRE SIGNALING section.

ROM COMMANDS

After the bus master has detected a presence pulse, it can issue a ROM command. These commands

operate on the unique 64–bit ROM codes of each slave device and allow the master to single out a

specific device if many are present on the 1-Wire bus. These commands also allow the master to

determine how many and what types of devices are present on the bus or if any device has experienced an

alarm condition. There are five ROM commands, and each command is 8 bits long. The master device

must issue an appropriate ROM command before issuing a DS18B20-PAR function command. A

flowchart for operation of the ROM commands is shown in Figure 10.

SEARCH ROM [F0h]

When a system is initially powered up, the master must identify the ROM codes of all slave devices on

the bus, which allows the master to determine the number of slaves and their device types. The master

learns the ROM codes through a process of elimination that requires the master to perform a Search ROM

4.7K

5 μA

Typ.

DS18B20-PAR 1-WIRE PORT

100 Ω

FET

= RECEIVE

= TRANSMIT

1-wire bus

Micro-

processor

Strong

Pullup

DS18B20-PAR

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cycle (i.e., Search ROM command followed by data exchange) as many times as necessary to identify all

of the slave devices. If there is only one slave on the bus, the simpler Read ROM command (see below)

can be used in place of the Search ROM process. For a detailed explanation of the Search ROM

procedure, refer to the iButton

Book of Standards at www.ibutton.com/ibuttons/standard.pdf. After

every Search ROM cycle, the bus master must return to Step 1 (Initialization) in the transaction sequence.

READ ROM [33h]

This command can only be used when there is one slave on the bus. It allows the bus master to read the

slave’s 64-bit ROM code without using the Search ROM procedure. If this command is used when there

is more than one slave present on the bus, a data collision will occur when all the slaves attempt to

respond at the same time.

MATCH ROM [55h]

The match ROM command followed by a 64–bit ROM code sequence allows the bus master to address a

specific slave device on a multi-drop or single-drop bus. Only the slave that exactly matches the 64–bit

ROM code sequence will respond to the function command issued by the master; all other slaves on the

bus will wait for a reset pulse.

SKIP ROM [CCh]

The master can use this command to address all devices on the bus simultaneously without sending out

any ROM code information. For example, the master can make all DS18B20-PARs on the bus perform

simultaneous temperature conversions by issuing a Skip ROM command followed by a Convert T [44h]

command. Note, however, that the Skip ROM command can only be followed by the Read Scratchpad

[BEh] command when there is one slave on the bus. This sequence saves time by allowing the master to

read from the device without sending its 64–bit ROM code. This sequence will cause a data collision on

the bus if there is more than one slave since multiple devices will attempt to transmit data simultaneously.

ALARM SEARCH [ECh]

The operation of this command is identical to the operation of the Search ROM command except that

only slaves with a set alarm flag will respond. This command allows the master device to determine if

any DS18B20-PARs experienced an alarm condition during the most recent temperature conversion.

After every Alarm Search cycle (i.e., Alarm Search command followed by data exchange), the bus master

must return to Step 1 (Initialization) in the transaction sequence. Refer to the OPERATION – ALARM

SIGNALING section for an explanation of alarm flag operation.

DS18B20-PAR FUNCTION COMMANDS

After the bus master has used a ROM command to address the DS18B20-PAR with which it wishes to

communicate, the master can issue one of the DS18B20-PAR function commands. These commands

allow the master to write to and read from the DS18B20-PAR’s scratchpad memory, initiate temperature

conversions and determine the power supply mode. The DS18B20-PAR function commands, which are

described below, are summarized in Table 4 and illustrated by the flowchart in Figure 11.

CONVERT T [44h]

This command initiates a single temperature conversion. Following the conversion, the resulting thermal

data is stored in the 2-byte temperature register in the scratchpad memory and the DS18B20-PAR returns

to its low-power idle state. Within 10 μs (max) after this command is issued the master must enable a

strong pullup on the 1-Wire bus for the duration of the conversion (t

conv

) as described in the PARASITE

POWER section.

WRITE SCRATCHPAD [4Eh]

This command allows the master to write 3 bytes of data to the DS18B20-PAR’s scratchpad. The first

data byte is written into the T

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