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AD7741YR-REEL7

P1-P3P4-P6P7-P9P10-P12
REV. 0
AD7741/AD7742
–4–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7741/AD7742 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
TIMING CHARACTERISTICS
1, 2, 3
Limit at T
MIN
, T
MAX
Parameter (B and Y Version) Units Conditions/Comments
f
CLKIN
6.144 MHz max
t
HIGH
/t
LOW
55/45 max Input Clock Mark/Space Ratio
45/55 min
t
1
9 ns typ f
CLOCK
Rising Edge to f
OUT
Rising Edge
t
2
4 ns typ f
OUT
Rise Time
t
3
4 ns typ f
OUT
Fall Time
t
4
t
HIGH
± 5 ns typ f
OUT
Pulsewidth
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figure 1.
Specifications subject to change without notice.
(V
DD
= +4.75 V to +5.25 V; V
REF
= +2.5 V. All specifications T
MIN
to T
MAX
unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= +25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3␣ V to +7 V
Analog Input Voltage to GND . . . . . . . . –5␣ V to V
DD
+ 0.3 V
Digital Input Voltage to GND . . . . . . . –0.3␣ V to V
DD
+ 0.3 V
Reference Input Voltage to GND . . . . –0.3 V to V
DD
+ 0.3 V
f
OUT
to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Automotive (Y Version) . . . . . . . . . . . . . . –40°C to +105°C
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance (8 Lead) . . . . . . . . . . . . . 125°C/W
θ
JA
Thermal Impedance (16 Lead) . . . . . . . . . . . . 117°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
SOIC Package
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance (8 Lead) . . . . . . . . . . . . . 157°C/W
θ
JA
Thermal Impedance (16 Lead) . . . . . . . . . . . . 125°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Temperature Package Package
Models Ranges Descriptions Options
AD7741BN –40°C to +85°C Plastic DIP N-8
AD7741BR –40°C to +85°C Small Outline R-8
AD7741YR –40°C to +105°C Small Outline R-8
AD7742BN –40°C to +85°C Plastic DIP N-16
AD7742BR –40°C to +85°C Small Outline R-16A
AD7742YR –40°C to +105°C Small Outline R-16A
CLKIN
f
OUT
t
HIGH
t
4
t
1
t
2
t
3
Figure 1. Timing Diagram
REV. 0
AD7741/AD7742
–5–
AD7741 PIN FUNCTION DESCRIPTION
Pin No. Mnemonic Function
1V
DD
Power Supply Input. These parts can be operated from +4.75 V to +5.25 V and the supply should
be adequately decoupled to GND.
2 GND Ground reference point for all circuitry on the part.
3 CLKOUT External Clock Output. When the master clock for the device is a crystal, the crystal is connected
between CLKIN and CLKOUT. When an external clock is applied to CLKIN, the CLKOUT pin
provides an inverted clock signal. This clock should be buffered if it is to be used as a clock source
elsewhere in the system.
4 CLKIN External Clock Input. The master clock for the device can be provided in the form of a crystal or an
external clock. A crystal may be tied across the CLKIN and CLKOUT pins. Alternatively, the
CLKIN pin may be driven by a CMOS-compatible clock and CLKOUT left unconnected. The
frequency of the master clock may be as high as 6 MHz.
5 REFIN/OUT This is the reference input to the core of the VFC and defines the span of the VFC. If this pin is left
unconnected, the internal 2.5 V reference is used. Alternatively, a precision external reference (e.g.,
REF192) may be used to overdrive the internal reference. The internal bandgap reference has a
high output impedance in order to allow it to be overdriven.
6V
IN
The analog input to the VFC. It has an input range from 0 V to V
REF
. This input is buffered so it
draws virtually no current from whatever source is driving it.
7 PD Active Low Power-Down pin. When this input is low, the part enters power-down mode where it
typically consumes 15 µA of current.
8f
OUT
Frequency Output. This pin provides the output of the synchronous VFC.
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
V
DD
f
OUT
AD7741
GND
PD
CLKOUT
V
IN
CLKIN
REFIN/OUT
REV. 0
AD7741/AD7742
–6–
AD7742 PIN FUNCTION DESCRIPTION
Pin No. Mnemonic Function
1f
OUT
Frequency Output. This pin provides the output of the synchronous VFC.
2V
DD
Power Supply Input. These parts can be operated from +4.75 V to +5.25 V and the supply should be
adequately decoupled to GND.
3 GND Ground reference point for all circuitry on the part.
4–5 A1, A0 Address Inputs used to select the input channel configuration.
6 CLKOUT External Clock Output. When the master clock for the device is a crystal, the crystal is connected be-
tween CLKIN and CLKOUT. When an external clock is applied to CLKIN, the CLKOUT pin
provides an inverted clock signal. This clock should be buffered if it is to be used as a clock source
elsewhere in the system.
7 CLKIN External Clock Input. The master clock for the device can be provided in the form of a crystal or an
external clock. A crystal may be tied across the CLKIN and CLKOUT pins. Alternatively, the CLKIN
pin may be driven by a CMOS-compatible clock and CLKOUT left unconnected. The frequency of the
master clock may be as high as 6 MHz.
8 UNI/BIP Control input which determines whether the device operates with differential bipolar analog input
signals or differential unipolar analog input signals.
9 REFOUT 2.5 V Voltage Reference Output. This can be tied directly to REFIN. It may also be used as a reference
to other parts of the system provided it is buffered first.
10 REFIN This is the Reference Input to the core of the VFC and defines the span of the VFC. A 2.5 V reference
is required at this pin. This may be provided by connecting it directly to REFOUT or by using a preci-
sion external reference (e.g., REF192).
11 V
IN
1 Buffered Analog Input Channel 1. This is either a pseudo-differential input with respect to V
IN
4 or it is
the positive input of a truly-differential input pair with respect to V
IN
2.
12 V
IN
2 Buffered Analog Input Channel 2. This is either a pseudo-differential input with respect to V
IN
4 or it is
the negative input of a truly-differential input pair with respect to V
IN
1.
13 V
IN
3 Buffered Analog Input Channel 3. This is the positive input of a truly-differential input pair with re-
spect to V
IN
4.
14 V
IN
4 Buffered Analog Input Channel 4. This is either the common for pseudo-differential input with respect
to V
IN
1 or V
IN
2 or it is the negative input of a truly-differential input pair with respect to V
IN
3.
15 GAIN Gain Select input that controls whether the gain on the analog front-end is X1 or X2.
16 PD Active Low Power-Down pin. When this input is low, the part enters power-down mode where it typi-
cally consumes 25 µA of current.
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
f
OUT
PD
AD7742
V
DD
GAIN
GND V
IN
4
A1 V
IN
3
A0 V
IN
2
CLKOUT V
IN
1
CLKIN
REFIN
UNI/BIP REFOUT
P1-P3P4-P6P7-P9P10-P12

AD7741YR-REEL7

Mfr. #:
Buy AD7741YR-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Voltage to Frequency & Frequency to Voltage Low-Cost SGL-Supply SGL-Ch Sync
Lifecycle:
New from this manufacturer.
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