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ADF4106BRUZ-R7
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P25
ADF4106
Data Sheet
Table
6
. Latch Summary
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2
(0)
C1
(0)
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
ABP1
ABP2
T1
T2
LDP
DB21
DB22
DB23
0
0
X
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2
(0)
C1
(1)
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
A6
DB21
DB22
DB23
G1
X
X
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2
(1)
C1
(0)
F1
PD1
M1
M2
M3
F3
P1
P2
CPI1
CPI2
CPI5
CPI6
TC4
PD2
F2
CPI3
CPI4
DB21
TC3
TC2
TC1
DB22
DB23
F4
F5
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2
(1)
C1
(1)
F1
PD1
M1
M2
M3
F3
P1
P2
CPI1
CPI2
CPI5
CPI6
TC4
PD2
F2
CPI3
CPI4
DB21
TC3
TC2
TC1
DB22
DB23
F4
F5
REFERENCE COUNTER LATCH
RESERVED
LOCK
DETECT
PRECISION
TEST
MODE BITS
ANTI-
BACKLASH
WIDTH
14-BIT REFERENCE COUNTER
CONTROL
BITS
RESERVED
13-BIT B COUNTER
6-BIT A COUNTER
CONTROL
BITS
N COUNTER LATCH
CP GAIN
FUNCTION LATCH
PRESCALER
VALUE
POWER-
DOWN 2
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
FASTLOCK
MODE
FASTLOCK
ENABLE
CP THREE-
STATE
PD
POLARITY
MUXOUT
CONTROL
POWER-
DOWN 1
COUNTER
RESET
CONTROL
BITS
PRESCALER
VALUE
POWER-
DOWN 2
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
FASTLOCK
MODE
FASTLOCK
ENABLE
CP THREE-
STATE
PD
POLARITY
MUXOUT
CONTROL
POWER-
DOWN 1
COUNTER
RESET
CONTROL
BITS
INITIALIZATION LATCH
02720-022
Rev.
F
| Pa
ge
12
of
24
Data Sheet
ADF4106
Table
7
. Reference Cou
nter Latch Map
LDP
0
1
ABP2
ABP1
0
0
2.9ns
0
1
1.3ns
1
0
6.0ns
1
1
2.9ns
R14
R13
R12
..........
R3
R2
R1
0
0
0
..........
0
0
1
1
0
0
0
..........
0
1
0
2
0
0
0
..........
0
1
1
3
0
0
0
..........
1
0
0
4
.
.
.
..........
.
.
.
.
.
.
.
..........
.
.
.
.
.
.
.
..........
.
.
.
.
1
1
1
..........
1
0
0
16380
1
1
1
..........
1
0
1
16381
1
1
1
..........
1
1
0
16382
1
1
1
..........
1
1
1
16383
X
= DON’T CARE
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2
(0)
C1 (0)
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
ABP1
ABP2
T1
T2
LDP
DB21
DB22
DB23
0
0
X
RESERVED
LOCK
DETECT
PRECISION
TEST
MODE BITS
ANTI-
BACKLASH
WIDTH
14-BIT REFERENCE COUNTER
CONTROL
BITS
DIVIDE RATIO
ANTIBACKLASH PULSE WIDTH
TEST MODE BITS
SHOULD BE SET
TO 00 FOR NORMAL
OPERATION.
OPERATION
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
BOTH OF THESE BITS
MUST BE SET TO 0 FOR
NORMAL OPERATION.
02720-023
Rev.
F
| Pa
ge
13
of
24
ADF4106
Data Sheet
Table
8
.
N (
A
,
B)
Counter Latch Map
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0)
C1 (1)
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
A6
DB21
DB22
DB23
G1
0
0
0
1
1
0
F4 (FUNCTION LATCH)
FASTLOCK ENABLE
1
1
A6
A5
..........
A2
A1
0
0
..........
0
0
0
0
0
..........
0
1
1
0
0
..........
1
0
2
0
0
..........
1
1
3
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
60
1
1
..........
0
1
61
1
1
..........
1
0
62
1
1
..........
1
1
63
X
X
B13
B12
B11
B3
B2
B1
0
0
0
..........
0
0
0
0
0
0
..........
0
0
1
0
0
0
..........
0
1
0
0
0
0
..........
0
1
1
3
.
.
.
..........
.
.
.
.
.
.
.
..........
.
.
.
.
.
.
.
..........
.
.
.
.
1
1
1
..........
1
0
0
8188
1
1
1
..........
1
0
1
8189
1
1
1
..........
1
1
0
8190
1
1
1
..........
1
1
1
8191
X = DON’T CARE
RESERVED
13-BIT B COUNTER
6-BIT A COUNTER
CONTROL
BITS
CP GAIN
A COUNTER
DIVIDE RATIO
B COUNTER DIVIDE RATIO
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS.
OPERATION
CP GAIN
CHARGE PUMP CURRENT
SETTING 1 IS PERMANENTLY USED.
CHARGE PUMP CURRENT
SETTING 2 IS PERMANENTLY USED.
CHARGE PUMP CURRENT
SETTING 1 IS USED.
CHARGE PUMP CURRENT IS
SWITCHED TO SETTING 2. THE
TIME SPENT IN SETTING 2 IS
DEPENDENT ON WHICH FASTLOCK
MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION.
N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION
LATCH. B MUST BE GREATER THAN OR EQUAL TO A. FOR
CONTINUOUSLY ADJACENT VALUES OF (N
×
F
REF
), AT THE
OUTPUT, N
MIN
IS (P
2
– P).
02720-024
Rev.
F
| Pa
ge
14
of
24
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P25
ADF4106BRUZ-R7
Mfr. #:
Buy ADF4106BRUZ-R7
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL Freq Synthesizer
Lifecycle:
New from this manufacturer.
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