ISSI
®
IS61C632A
8
Integrated Silicon Solution, Inc.
SR001-1B
05/18/98
READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-4 -5 -6 -7 -8
Symbol Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 8 — 10 — 12 — 13 — 15 — ns
tKH Clock High Time 4 — 4 — 4 — 6 — 6 — ns
tKL Clock Low Time 4 — 4 — 4 — 6 — 6 — ns
tKQ Clock Access Time — 4 — 5 — 6 — 7 — 8 ns
tKQX
(2)
Clock High to Output Invalid 1.5 — 1.5 — 2 — 2 — 2 — ns
tKQLZ
(2,3)
Clock High to Output Low-Z 0 — 0 — 0 — 0 — 0 — ns
tKQHZ
(2,3)
Clock High to Output High-Z 1.5 4 1.5 5 2 6 2 6 2 6 ns
tOEQ Output Enable to Output Valid — 4 — 5 — 6 — 6 — 6 ns
tOEQX
(2)
Output Disable to Output Invalid 0 — 0 — 0 — 0 — 0 — ns
tOELZ
(2,3)
Output Enable to Output Low-Z 0 — 0 — 0 — 0 — 0 — ns
tOEHZ
(2,3)
Output Disable to Output High-Z — 4.5 — 4.8 — 6 — 6 — 6 ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tCFG Configuration Setup
(1)
25 — 35 — 45 — 66.7 — 80 — ns
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with the load in Figure 2.
