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FOD2200T

P1-P3P4-P6P7-P9P10-P12P13-P15
©2004 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD2200 Rev. 1.0.4 7
FOD2200 — Low Input Current Logic Gate Optocouplers
Test Circuits (Continued)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
Fig. 3. Test Circuit and Typical Waveforms for Common Mode Transient Immunity
50 V
OUTPUT
V
O
* SEE NOTE 6.
0 V
V
OH
V
OL
V
O
(MAX.)*
V
O
(MIN.)*
SWITCH AT A: I
F
= 1.6mA
SWITCH AT B: I
F
= 0mA
V
CM
7
1
4
5
6
8
FOD2200
0.1 µF
BYPASS
OUTPUT V
O
MONITORING
NODE
V
CC
R
IN
2
3
V
FF
A
B
–+
V
CM
PULSE GENERATOR
V
CC
GND
FOD2200
DATA
INPUT
D1 (1N4150) REQUIRED FOR
ACTIVE PULL-UP DRIVER.
1.1kΩ
V
CC1
(+5 V)
V
CC
GND
D1
TTL OR
LSTTL
Figure 4. Recommended LSTTL to LSTTL Circuit
Figure 6. Recommended LED Drive Circuit
Figure 5. LSTTL to CMOS Interface Circuit
Figure 7. Series LED Drive with Open Collector Gate
(4.7kΩ Resistor Shunts I
OH
from the LED)
120pF
1
2
3
4
8
7
6
5
1
2
FOD2200
DATA
INPUT
TTL OR
LSTTL
V
CC2
(+5V)
UP TO 16
LSTTL
LOADS
OR 4 TTL
LOADS
1.1
kΩ
V
CC1
(+5V)
DATA
OUTPUT
TOTEM
POLE
OUTPUT
GATE
V
CC
GND
120pF (OPTIONAL*)
*The 120pF capacitor may be omitted in applications where 500ns propagation delay is sufficient.
FOD2200
DATA
INPUT
TTL OR
LSTTL
1.1
kΩ
V
CC
(+5 V)
OPEN
COLLECTOR
GATE
V
CC
GND
4.7kΩ
120pF (OPTIONAL*)
1
2
FOD2200
DATA
INPUT
TTL OR
LSTTL
V
CC2
(4.5V TO 20V)
1.1
kΩ
V
CC1
(+5V)
DATA
OUTPUT
TOTEM
POLE
OUTPUT
GATE
V
CC
GND
CMOS
V
CC2
5V
10V
15V
20V
R
L
1.1kΩ
2.37kΩ
3.83kΩ
5.11kΩ
R
L
1
2
3
4
8
7
6
5
©2004 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD2200 Rev. 1.0.4 8
FOD2200 — Low Input Current Logic Gate Optocouplers
Typical Performance Curves
I
F(ON)
I
F(OFF)
Figure 9. Output Voltage vs. Input Forward Current
I
F
– INPUT FORWARD CURRENT (mA)
0.0 0.2 0.4 0.6 0.8 1.0 1.2
V
O
– Output Voltage (V)
0
1
2
3
4
5
CC
I
O
= -2.6mA
V
T
A
= 25°C
I
O
= 6.4mA
= 4.5V
Figure 10. Input Threshold Current vs. Ambient Temperature
T
A
– Ambient Temperature (°C)
-40 -20 0 20 40 60 80 100
T
A
– AMBIENT TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100
INPUT CURRENT THRESHOLD (mA)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
I
F
(ON)
I
F
(OFF)
V
CC
= 5V, 20V
Figure 11. Logic Low Output Voltage vs. Ambient Temperature
V
OL
– LOGIC LOW OUTPUT VOLTAGE (V)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
V
CC
= 4.5V
I
F
= 0 mA
I
O
= 6.4 mA
Figure 12. Logic High Output Voltage vs. Supply Voltage
V
CC
– SUPPLY VOLTAGE (V)
048121620
V
OH
– LOGIC HIGH OUTPUT VOLTAGE (V)
0
4
8
12
16
20
I
O
= -2.6 mA
T
A
= 25°C
I
F
≥ I
F
(ON)
Figure 13. Logic High Output Current vs. Ambient Temperature
T
A
– AMBIENT TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100
I
OH
– LOGIC HIGH OUTPUT CURRENT (mA)
-7
-6
-5
-4
-3
-2
-1
0
V
CC
= 4.5V
I
F
= 5 mA
V
O
= 2.7V
V
O
= 2.4V
Figure 14. Propagation Delay vs Ambient Temperature
T
A
– AMBIENT TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100
T
A
– AMBIENT TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100
t
P
– PROPAGATION DELAY (µs)
60
100
140
180
220
260
V
CC
t
PHL
, I
F
t
PHL
, I
F
= 5mA
= 5V
See Figure 1.
= 1.6mA
t
PLH
, I
F
= 1.6mA–5mA
t
PHL
, I
F
C1 (120pF) Peaking Capacitor Is Used.
Figure 15. Rise, Fall Time vs Ambient Temperature
t
f
, tr – RISE, FALL TIME (µs)
0
40
80
120
160
200
V
CC
I
F
t
f
t
r
= 5V
= 1.6mA
Figure 8. Input Forward Current vs Forward Voltage
V
F
– FORWARD VOLTAGE (V)
0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7
I
F
– FORWARD CURRENT (mA)
0.001
0.01
0.1
1
10
100
T
A
= 85°C
T
A
= 70°C
T
A
= 25°C
T
A
= 0°C
T
A
= -40°C
= 3mA
©2004 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD2200 Rev. 1.0.4 9
FOD2200 — Low Input Current Logic Gate Optocouplers
Package Dimensions
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
Through Hole
Surface Mount – 0.3" Lead Spacing (Option S)
Note:
All dimensions are in inches (millimeters)
0.4" Lead Spacing (Option T)
8-Pin Surface Mount DIP – Land Pattern
(Option S)
0.200 (5.08)
MAX
0.100 (2.54) TYP
0.022 (0.56)
0.016 (0.41)
0.020 (0.51)
MIN
0.390 (9.91)
0.370 (9.40)
0.270 (6.86)
0.250 (6.35)
3
0.070 (1.78)
0.045 (1.14)
0.156 (3.94)
0.144 (3.68)
241
56 7
8
0.300 (7.62)
TYP
0.154 (3.90)
0.120 (3.05)
0.016 (0.40)
0.008 (0.20)
15° MAX
PIN 1
ID.
SEATING PLANE
0.270 (6.86)
0.250 (6.35)
0.390 (9.91)
0.370 (9.40)
0.022 (0.56)
0.016 (0.41)
0.100 (2.54)
TYP
0.020 (0.51)
MIN
0.070 (1.78)
0.045 (1.14)
0.156 (3.94)
0.144 (3.68)
0.300 (7.62)
TYP
0.405 (10.30)
MAX.
0.315 (8.00)
MIN
0.015 (0.40) MIN
Both Sides
32 14
567
8
0.016 (0.40)
0.008 (0.20)
PIN 1
ID.
0.200 (5.08)
MAX
0.100 (2.54) TYP
0.022 (0.56)
0.031 (0.78)
0.016 (0.41)
0.020 (0.51)
MIN
0.390 (9.91)
0.370 (9.40)
0.270 (6.86)
0.250 (6.35)
3
0.070 (1.78)
0.156 (3.94)
0.144 (3.68)
0.045 (1.14)
241
56 7
8
0.400 (10.16)
TYP
0.154 (3.90)
0.120 (3.05)
0.016 (0.40)
0.008 (0.20)
0° to 15°
PIN 1
ID.
SEATING PLANE
0.070 (1.78)
0.060 (1.52)
0.030 (0.76)
0.100 (2.54)
0.295 (7.49)
0.415 (10.54)
0.200 (5.08)
MAX
P1-P3P4-P6P7-P9P10-P12P13-P15

FOD2200T

Mfr. #:
Buy FOD2200T
Manufacturer:
ON Semiconductor / Fairchild
Description:
High Speed Optocouplers Low Input Current Logic Gate Coupler
Lifecycle:
New from this manufacturer.
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