PCA9541A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 24 April 2014 17 of 45
NXP Semiconductors
PCA9541A
2-to-1 I
2
C-bus master selector with interrupt logic and reset
[1] Default values are the same for PCA9541A/01 and PCA9541A/03.
[2] Reading the Interrupt Status Register does not clear the MYTEST, NMYTEST or the INTIN bits. They are cleared if:
INT_IN
line goes HIGH for INTIN bit
TESTON bit is cleared for MYTEST bit
NTESTON bit is cleared for NMYTEST bit
[3] Interrupt on a master is cleared after TESTON bit is cleared by the same master or NTESTON bit is cleared by the other master.
[4] BUSINIT, BUSOK and BUSLOST bits in the Interrupt Status Register get cleared after a read of the same register is done. Precisely, the
register gets cleared on the second clock pulse during the read operation.
[5] If the interrupt condition remains on INT_IN
after the read sequence, another interrupt will be generated (if the interrupt has not been
masked).
7.5 Power-on reset
When power is applied to V
DD
, an internal power-on reset holds the PCA9541A in a reset
condition until V
DD
has reached V
POR
. At this point, the reset condition is released and the
internal registers are initialized to their default states, with:
• PCA9541A/01: default Channel 0 (no STOP detect)
After power-up and/or insertion of the device in the main I
2
C-bus, the upstream
Channel 0 and the downstream slave channel are connected together.
• PCA9541A/03: default ‘no channel’ (no STOP detect)
After power-up and/or insertion of the device in the main I
2
C-bus, no channel will be
connected to the downstream channel. The device is ready to receive a START
condition and its address by a master.
If either register writes to its Control Register, then the connection between the
upstream and the downstream channels is determined by the values on the Control
Registers.
Thereafter, V
DD
must be lowered below 0.2 V for at least 5 s in order to reset the device.
2BUSOK
[4]
R only 0* no interrupt generated by bus sensor function
1 interrupt generated by bus sensor function (masked when bus
recovery/initialization requested) - Bus was not idle when the switch occurred
1 BUSINIT
[4]
R only 0* no interrupt generated by the bus recovery/initialization function
1 interrupt generated by the bus recovery/initialization function;
recovery/initialization done
0INTIN
[2]
R only 0* no interrupt on interrupt input (INT_IN)
[5]
1 interrupt on interrupt input (INT_IN)
[5]
Table 14. Register 2 - Interrupt Status (ISTAT) register bit description …continued
Legend: * default value
Bit Symbol Access Value
[1]
Description
