FEDR44V100A-01
MR44V100A
14/18
•POWER-ON AND POWER-OFF CHARACTERISTICS
(Under recommended operating conditions)
Parameter Symbol Min. Max. Unit Note
Power-On SCL,SDA High Hold Time
t
VHEL
100 ⎯ ns 1, 2
Power-Off SCL, SDA High Hold Time
t
EHVL
0 ⎯ ns 1
Power-On Interval Time
t
VLVH
0 ⎯ μs 2
V
CC
Power-On ramp rate
tr 30 μs/V
V
CC
Power-Off ramp rate
tf 30 μs/V
Notes:
1. To prevent an erroneous operation, be sure to maintain SCL=SDA="H", and set the FeRAM in an inactive
state (standby mode) before and after power-on and power-off.
2. Powering on at the intermediate voltage level will cause an erroneous operation; thus, be sure to power up
from 0 V.
3. Enter all signals at the same time as power-on or enter all signals after power-on.
•Power-On and Power-Off Sequences
・After Power-Off, terminal state
When MR44V100A only goes power-off while the other IC’s on I2C bus are active, all the input pins including
I/O pin of MR44V100A must be GND level.
(When to reduce stand-by current while SCL or SDA bus are active, recommend the use of SLEEP
mode.)
SCL,SD
SCL,SDA
0
V
IL
Max.
V
CC
Min.
V
CC
V
IH
Min.
0V
V
IL
Max.
V
CC
Min.
V
CC
V
IH
Min.
t
VHEL
t
VLVH
t
EHVL
t
r
t
f
