ICS851S201CKI REVISION A SEPTEMBER 6, 2013 2 ©2013 Integrated Device Technology, Inc.
ICS851S201I Data Sheet 2:1 DIFFERENTIAL-TO-HCSL MULTIPLEXER
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1 CLK0 Input Pulldown Non-inverting differential HCSL clock input.
2 nCLK0 Input
Pullup/
Pulldown
Inverting differential HCSL clock input. V
DD
/2 default when left floating.
3 CLK1 Input Pulldown Non-inverting differential HCSL clock input.
4 nCLK1 Input
Pullup/
Pulldown
Inverting differential HCSL clock input. V
DD
/2 default when left floating.
5, 13 V
DD
Power Positive supply pins.
6 LLAR Input Pulldown
Low Level Alarm Reset. When HIGH, resets LLA latch. Must be LOW to
allow LLA to set. LVCMOS/LVTTL interface levels.
7 LLA Output
Low Level Alarm. When HIGH, low level input has been detected on
selected differential input (latched).
8, 16 GND Power Power supply ground.
9, 10
Q1, nQ1
Output Differential output pair. HCSL interface levels.
11, 12
Q0, nQ0
Output Differential output pair. HCSL interface levels.
14 IREF Input
External fixed precision resistor (475from this pin to ground provides a
reference current used for differential current-mode Qx, nQx clock outputs.
15 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW,
selects CLK0, nCLK0 inputs. LVCMOS/LVTTL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 2 pF
R
PULLDOWN
Input Pulldown Resistor 50 k
R
PULLUP
Input Pullup Resistor 50 k
