ICS851S201CKI REVISION A SEPTEMBER 6, 2013 7 ©2013 Integrated Device Technology, Inc.
ICS851S201I Data Sheet 2:1 DIFFERENTIAL-TO-HCSL MULTIPLEXER
Parameter Measurement Information, continued
Propagation Delay
Differential Measurement Points for Duty Cycle/Period
Single-ended Measurement Points for Absolute Cross
Point and Swing
Single-ended Measurement Points for Delta Cross Point
Output Rise/Fall Edge Rate
t
PD
nQx
Qx
nCLKx
CLKx
ICS851S201CKI REVISION A SEPTEMBER 6, 2013 8 ©2013 Integrated Device Technology, Inc.
ICS851S201I Data Sheet 2:1 DIFFERENTIAL-TO-HCSL MULTIPLEXER
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
CLK/nCLK Inputs
For applications not requiring the use of a differential input, both the
CLK and nCLK pins can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
LVCMOS Control Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
Outputs:
Differential Outputs
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
Differential Clock Input Interface
The CLK /nCLK accepts HCSL and other differential signals. Both
differential signals must meet the V
PP
and V
CMR
input requirements.
Figure 2 shows interface examples for the CLK/nCLK input driven by
the most common driver types. The input interfaces suggested here
are examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements.
Figure 2. CLK/nCLK Input Driven by a 3.3V HCSL Driver
H
CSL
*R
3
*
R4
C
L
K
n
C
L
K
3
.
3V
.
Diff
e
r
e
nti
a
l
In
p
u
t
ICS851S201CKI REVISION A SEPTEMBER 6, 2013 9 ©2013 Integrated Device Technology, Inc.
ICS851S201I Data Sheet 2:1 DIFFERENTIAL-TO-HCSL MULTIPLEXER
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 3. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
SOLDERSOLDER
PINPIN EXPOSED HEAT SLUG
PIN PAD PIN PADGROUND PLANE LAND PATTERN
(GROUND PAD)
THERMAL VIA

851S201CKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 2 to 1 Diff-to-HCSL Multi w/Low Alarm
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet