10
LTC2400
an order of magnitude. The part remains in the sleep state
as long as CS is logic HIGH. The conversion result is held
indefinitely in a static shift register while the converter is
in the sleep state.
Once CS is pulled low, the device begins outputting the
conversion result. There is no latency in the conversion
result. The data output corresponds to the conversion just
performed. This result is shifted out on the serial data out
pin (SDO) under the control of the serial clock (SCK). Data
is updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK, see Figure 3.
The data output state is concluded once 32 bits are read
out of the ADC or when CS is brought HIGH. The device
automatically initiates a new conversion cycle and the
cycle repeats.
Through timing control of the CS and SCK pins, the
LTC2400 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require program-
ming configuration registers; moreover, they do not dis-
turb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.
Conversion Clock
A major advantage delta-sigma converters offer over
conventional type converters is an on-chip digital filter
(commonly known as Sinc or Comb filter). For high
resolution, low frequency applications, this filter is typi-
cally designed to reject line frequencies of 50 or 60Hz plus
their harmonics. In order to reject these frequencies in
excess of 110dB, a highly accurate conversion clock is
required. The LTC2400 incorporates an on-chip highly
accurate oscillator. This eliminates the need for external
frequency setting components such as crystals or oscilla-
tors. Clocked by the on-chip oscillator, the LTC2400
rejects line frequencies (50 or 60Hz ±2%) a minimum of
110dB.
Ease of Use
The LTC2400 data output has no latency, filter settling or
redundant data associated with the conversion cycle.
There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
an analog input voltage is easy.
The LTC2400 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation de-
scribed above. The advantage of continuous calibration is
extreme stability of offset and full-scale readings with re-
spect to time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2400 automatically enters an internal reset state
when the power supply voltage V
CC
drops below approxi-
mately 2.2V. This feature guarantees the integrity of the
conversion result and of the serial interface mode selec-
tion which is performed at the initial power-up. (See the
2-wire I/O sections in the Serial Interface Timing Modes
section.)
When the V
CC
voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with duration of approximately 0.5ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2400 starts a normal conversion cycle and
follows the normal succession of states described above.
The first conversion result following POR is accurate
within the specifications of the device.
Reference Voltage Range
The LTC2400 can accept a reference voltage from 0V to
V
CC
. The converter output noise is determined by the
thermal noise of the front-end circuits, and as such, its
value in microvolts is nearly constant with reference
voltage. A decrease in reference voltage will not signifi-
cantly improve the converter’s effective resolution. On the
other hand, a reduced reference voltage will improve the
overall converter INL performance. The recommended
range for the LTC2400 voltage reference is 100mV to V
CC
.
Input Voltage Range
The converter is able to accommodate system level offset
and gain errors as well as system level overrange situa-
tions due to its extended input range, see Figure 2. The
LTC2400 converts input signals within the extended input
range of –0.125 • V
REF
to 1.125 • V
REF
.
APPLICATIONS INFORMATION
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11
LTC2400
APPLICATIONS INFORMATION
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2400 F02
V
CC
+ 0.3V
9/8V
REF
V
REF
1/2V
REF
0.3V
1/8V
REF
0
NORMAL
INPUT
RANGE
EXTENDED
INPUT
RANGE
ABSOLUTE
MAXIMUM
INPUT
RANGE
Figure 2. LTC2400 Input Range
For large values of V
REF
this range is limited by the
absolute maximum voltage range of – 0.3V to (V
CC
+ 0.3V).
Beyond this range the input ESD protection devices begin
to turn on and the errors due to the input leakage current
increase rapidly.
Input signals applied to V
IN
may extend below ground by
300mV and above V
CC
by 300mV. In order to limit any
fault current, a resistor of up to 5k may be added in series
with the V
IN
pin without affecting the performance of the
device. In the physical layout, it is important to maintain
the parasitic capacitance of the connection between this
series resistance and the V
IN
pin as low as possible;
therefore, the resistor should be located as close as
practical to the V
IN
pin. The effect of the series resistance
on the converter accuracy can be evaluated from the
curves presented in the Analog Input/Reference Current
section. In addition a series resistor will introduce a
temperature dependent offset error due to the input leak-
age current. A 1nA input leakage current will develop a
1ppm offset error on a 5k resistor if V
REF
= 5V. This error
has a very strong temperature dependency.
Output Data Format
The LTC2400 serial output data stream is 32 bits long. The
first 4 bits represent status information indicating the
sign, input range and conversion state. The next 24 bits are
the conversion result, MSB first. The remaining 4 bits are
sub LSBs beyond the 24-bit level that may be included in
averaging or discarded without loss of resolution.
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0, this
bit is LOW. The sign bit changes state during the zero code.
Bit 28 (forth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0␣ ␣V
IN
V
REF
, this bit is LOW. If the input is outside the
normal input range, V
IN
> V
REF
or V
IN
< 0, this bit is HIGH.
The function of these bits is summarized in Table 1.
Table 1. LTC2400 Status Bits
Bit 31 Bit 30 Bit 29 Bit 28
Input Range EOC DMY SIG EXR
V
IN
> V
REF
0 011
0 < V
IN
V
REF
0 010
V
IN
= 0
+
/0
0 0 1/0 0
V
IN
< 0 0 001
Bit 27 (fifth output bit) is the most significant bit (MSB).
Bits 27-4 are the 24-bit conversion result MSB first.
Bit 4 is the least significant bit (LSB).
Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may
be included in averaging or discarded without loss of
resolution.
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the first
rising edge of SCK. Bit 30 is shifted out of the device on the
first falling edge of SCK. The final data bit (Bit 0) is shifted
12
LTC2400
APPLICATIONS INFORMATION
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Table 2. LTC2400 Output Data Format
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 4 Bit 3-0
Input Voltage EOC DMY SIG EXR MSB LSB SUB LSBs*
V
IN
> 9/8 • V
REF
001100011...1X
9/8 • V
REF
001100011...1X
V
REF
+ 1LSB 0 0 1 1 0 0 0 0 0 ... 0 X
V
REF
001011111...1X
3/4V
REF
+ 1LSB 0 0 1 0 1 1 0 0 0 ... 0 X
3/4V
REF
001010111...1X
1/2V
REF
+ 1LSB 0 0 1 0 1 0 0 0 0 ... 0 X
1/2V
REF
001001111...1X
1/4V
REF
+ 1LSB 0 0 1 0 0 1 0 0 0 ... 0 X
1/4V
REF
001000111...1X
0
+
/0
0 0 1/0** 0 0 0 0 0 0 ... 0 X
–1LSB 0 0 0111 1 11...1 X
–1/8 • V
REF
000111100...0X
V
IN
< –1/8 • V
REF
000111100...0X
*The sub LSBs are valid conversion results beyond the 24-bit level that may be included in averaging or discarded without loss of resolution.
**The sign bit changes state during the 0 code.
Figure 3. Output Data Timing
out on the falling edge of the 31st SCK and may be latched
on the rising edge of the 32nd SCK pulse. On the falling
edge of the 32nd SCK pulse, SDO goes HIGH indicating a
new conversion cycle has been initiated. This bit serves as
EOC (Bit 31) for the next conversion cycle. Table 2 sum-
marizes the output data format.
As long as the voltage on the V
IN
pin is maintained within
the –0.3V to (V
CC
+ 0.3V) absolute maximum operating
range, a conversion result is generated for any input value
from –0.125 • V
REF
to 1.125 • V
REF
.
For input voltages
greater than 1.125 • V
REF
, the conversion result is clamped
to the value corresponding to 1.125 • V
REF
. For input
voltages below –0.125 • V
REF
, the conversion result is
clamped to the value corresponding to –0.125 • V
REF
.
Frequency Rejection Selection (F
O
Pin Connection)
The LTC2400 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and all its
harmonics for 50Hz ±2% or 60Hz ±2%. For 60Hz rejec-
tion, F
O
(Pin 8) should be connected to GND (Pin 4) while
for 50Hz rejection the F
O
pin should be connected to V
CC
(Pin␣ 1).
MSBEXTSIG“0”
1 2 3 4 5 272832
BIT 0BIT 27 BIT 4
LSB
24
BIT 28BIT 29BIT 30
SDO
SCK
CS
EOC
BIT 31
SLEEP DATA OUTPUT CONVERSION
2400 F03
Hi-Z

LTC2400CS8#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 24-B Pwr No Lat Delta-Sigma ADC in SO-
Lifecycle:
New from this manufacturer.
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