Programmable Skew Clock Buffer
CY7B991
CY7B992
Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600
Document #: 38-07138 Rev. ** Revised September 26, 2001
92
Features
All output pair skew <100 ps typical (250 max.)
3.75- to 80-MHz output operation
User-selectable output functions
Selectable skew to 18 ns
Inverted and non-inverted
Operation at
1
2
and
1
4
input frequency
Operation at 2x and 4x input frequency (input as low
as 3.75 MHz)
Zero input to output delay
50% duty-cycle outputs
Outputs drive 50 terminated lines
Low operating current
32-pin PLCC/LCC package
Jitter < 200 ps peak-to-peak (< 25 ps RMS)
Compatible with a Pentium-based processor
Functional Description
The CY7B991 and CY7B992 Programmable Skew Clock Buff-
ers (PSCB) offer user-selectable control over system clock
functions. These multiple-output clock drivers provide the sys-
tem integrator with functions necessary to optimize the timing
of high-performance computer systems. Eight individual driv-
ers, arranged as four pairs of user-controllable outputs, can
each drive terminated transmission lines with impedances as
low as 50 while delivering minimal and specified output skews
and full-swing logic levels (CY7B991 TTL or CY7B992 CMOS).
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are deter-
mined by the operating frequency with outputs able to skew up
to ±6 time units from their nominal zero skew position. The com-
pletely integrated PLL allows external load and transmission line
delay effects to be canceled. When this zero delay capability of the
PSCB is combined with the selectable output skew functions, the
user can create output-to-output delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility mini-
mizes clock distribution difficulty while allowing maximum sys-
tem clock speed and flexibility.
Pentium is a trademark of Intel Corporation.
Logic Block Diagram Pin Configuration
7B9911
7B9912
TEST
FB
REF
VCO AND
TIME UNIT
GENERATOR
FS
SELECT
INPUTS
(THREE
LEVEL)
SKEW
SELECT
MATRIX
1234323130
17161514 18 19 20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
3F0
FS
V
REF
GND
TEST
2F1
FB
2Q1
2Q0
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
CCQ
2F0
GND
1F1
1F0
V
CCN
1Q0
1Q1
GND
GND
3Q1
3Q0
CCN
V
CCN
V
3F1
4F0
4F1
V
CCQ
V
CCN
4Q1
4Q0
GND
GND
PLCC/LCC
CY7B991
CY7B992
FILTER
PHASE
FREQ
DET
CY7B991
CY7B992
Document #: 38-07138 Rev. ** Page 2 of 15
Block Diagram Description
Phase Frequency Detector and Filter
These two blocks accept inputs from the reference frequency
(REF) input and the feedback (FB) input and generate correc-
tion information to control the frequency of the Voltage-Con-
trolled Oscillator (VCO). These blocks, along with the VCO,
form a Phase-Locked Loop (PLL) that tracks the incoming
REF signal.
VCO and Time Unit Generator
The VCO accepts analog control inputs from the PLL filter
block and generates a frequency that is used by the time unit
generator to create discrete time units that are selected in the
skew select matrix. The operational range of the VCO is de-
termined by the FS control pin. The time unit (t
U
) is determined
by the operating frequency of the device and the level of the
FS pin as shown in Table 1.
Skew Select Matrix
The skew select matrix is comprised of four independent sec-
tions. Each section has two low-skew, high-fanout drivers
(xQ0, xQ1), and two corresponding three-level function select
(xF0, xF1) inputs. Table 2 below shows the nine possible out-
put functions for each section as determined by the function
select inputs. All times are measured with respect to the REF
input assuming that the output connected to the FB input has
0t
U
selected.
Pin Definitions
Signal
Name I/O Description
REF I Reference frequency input. This input supplies the frequency and timing against which all functional
variation is measured.
FB I PLL feedback input (typically connected to one of the eight outputs).
FS I Three-level frequency range select. See Table 1.
1F0, 1F1 I Three-level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2.
2F0, 2F1 I Three-level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2.
3F0, 3F1 I Three-level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2.
4F0, 4F1 I Three-level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2.
TEST I Three-level select. See test mode section under the block diagram descriptions.
1Q0, 1Q1 O Output pair 1. See Table 2.
2Q0, 2Q1 O Output pair 2. See Table 2.
3Q0, 3Q1 O Output pair 3. See Table 2.
4Q0, 4Q1 O Output pair 4. See Table 2.
V
CCN
PWR Power supply for output drivers.
V
CCQ
PWR Power supply for internal circuitry.
GND PWR Ground.
Table 1. Frequency Range Select and t
U
Calculation
[1]
FS
[2, 3]
f
NOM
(MHz)
where N =
Approximate
Frequency (MHz) At
Which t
U
= 1.0 nsMin. Max.
LOW 15 30 44 22.7
MID 25 50 26 38.5
HIGH 40 80 16 62.5
t
U
1
f
NOM
N×
------------------------=
Table 2. Programmable Skew Configurations
[1]
Function Selects Output Functions
1F1, 2F1,
3F1, 4F1
1F0, 2F0,
3F0, 4F0
1Q0, 1Q1,
2Q0, 2Q1 3Q0, 3Q1 4Q0, 4Q1
LOW LOW 4t
U
Divide by 2 Divide by 2
LOW MID 3t
U
6t
U
6t
U
LOW HIGH 2t
U
4t
U
4t
U
MID LOW 1t
U
2t
U
2t
U
MID MID 0t
U
0t
U
0t
U
MID HIGH +1t
U
+2t
U
+2t
U
HIGH LOW +2t
U
+4t
U
+4t
U
HIGH MID +3t
U
+6t
U
+6t
U
HIGH HIGH +4t
U
Divide by 4 Inverted
Notes:
1. For all three-state inputs, HIGH indicates a connection to V
CC
, LOW
indicates a connection to GND, and MID indicates an open connection.
Internal termination circuitry holds an unconnected input to V
CC
/2.
2. The level to be set on FS is determined by the normal operating fre-
quency (f
NOM
) of the V
CO
and Time Unit Generator (see Logic Block
Diagram). Nominal frequency (f
NOM
) always appears at 1Q0 and the
other outputs when they are operated in their undivided modes (see
Table 2). The frequency appearing at the REF and FB inputs will be f
NOM
when the output connected to FB is undivided. The frequency of the REF
and FB inputs will be f
NOM
/2 or f
NOM
/4 when the part is configured for a
frequency multiplication by using a divided output as the FB input.
3. When the FS pin is selected HIGH, the REF input must not transition
upon power-up until V
CC
has reached 4.3V.
CY7B991
CY7B992
Document #: 38-07138 Rev. ** Page 3 of 15
Test Mode
The TEST input is a three-level input. In normal system oper-
ation, this pin is connected to ground, allowing the
CY7B991/CY7B992 to operate as explained briefly above (for
testing purposes, any of the three-level inputs can have a re-
movable jumper to ground, or be tied LOW through a 100
resistor. This will allow an external tester to change the state
of these pins.)
If the TEST input is forced to its MID or HIGH state, the device
will operate with its internal phase locked loop disconnected,
and input levels supplied to REF will directly control all outputs.
Relative output to output functions are the same as in normal
mode.
In contrast with normal operation (TEST tied LOW). All outputs
will function based only on the connection of their own function
select inputs (xF0 and xF1) and the waveform characteristics
of the REF input.
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................65
°C to +150°C
Ambient Temperature with
Power Applied ............................................ 55°C to +125°C
Supply Voltage to Ground Potential ...............0.5V to +7.0V
DC Input Voltage ............................................0.5V to +7.0V
Output Current into Outputs (LOW)............................. 64 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output
[4]
t
0
6t
U
t
0
5t
U
t
0
4t
U
t
0
3t
U
t
0
2t
U
t
0
1t
U
t
0
t
0
+1t
U
t
0
t
0
t
0
t
0
t
0
+2t
U
+3t
U
+4t
U
+5t
U
+6t
U
FBInput
REFInput
6t
U
4t
U
3t
U
2t
U
1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
+6t
U
DIVIDED
INVERT
LM
LH
(N/A)
ML
(N/A)
MM
(N/A)
MH
(N/A)
HL
HM
LL/HH
HH
3Fx
4Fx
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
(N/A)
1Fx
2Fx
7B9913
Operating Range
Range
Ambient
Temperature V
CC
Commercial 0°C to +70°C 5V ± 10%
Industrial 40°C to +85°C 5V ± 10%
Military
[5]
55°C to +125°C 5V ± 10%
Notes:
4. FB connected to an output selected for zero skew (i.e., xF1 = xF0 =
MID).
5. Indicates case temperature.

CY7B991-2JC

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL 5V 80MHz 8 TLL COM Programable
Lifecycle:
New from this manufacturer.
Delivery:
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