NB100LVEP91DWG

© Semiconductor Components Industries, LLC, 2016
June, 2018 Rev. 20
1 Publication Order Number:
NB100LVEP91/D
NB100LVEP91
2.5 V/3.3 V Any Level
Positive Input to
-2.5 V/-3.3 V LVNECL
Output Translator
Description
The NB100LVEP91 is a triple any level positive input to NECL
output translator. The device accepts LVPECL, LVTTL, LVCMOS,
HSTL, CML or LVDS signals, and translates them to differential
LVNECL output signals (2.5 V / 3.3 V).
To accomplish the level translation the LVEP91 requires three
power rails. The V
CC
pins should be connected to the positive power
supply, and the V
EE
pin should be connected to the negative power
supply. The GND pins are connected to the system ground plane. Both
V
EE
and V
CC
should be bypassed to ground via 0.01 mF capacitors.
Under open input conditions, the D
input will be biased at V
CC
/2
and the D input will be pulled to GND. These conditions will force the
Q outputs to a low state, and Q outputs to a high state, which will
ensure stability.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
Maximum Input Clock Frequency > 2.0 GHz Typical
Maximum Input Data Rate > 2.0 Gb/s Typical
500 ps Typical Propagation Delay
Operating Range:
V
CC
= 2.375 V to 3.8 V; V
EE
= 2.375 V to 3.8 V; GND = 0 V
Q Output will Default LOW with Inputs Open or at GND
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
MARKING DIAGRAMS*
SOIC20 WB
DW SUFFIX
CASE 751D05
1
20
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb-Free Package
N100
VP91
ALYWG
G
1
24
QFN24
MN SUFFIX
CASE 485L01
24 1
20
1
NB100LVEP91
AWLYYWWG
www.onsemi.com
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D
.
ORDERING INFORMATION
Device Package Shipping
NB100LVEP91DWG SOIC20 WB
(Pb-Free)
38 Units/Tube
NB100LVEP91DWR2G SOIC20 WB
(Pb-Free)
1000/Tape & Reel
QFN24
(Pb-Free)
NB100LVEP91MNR2G 3000/Tape & Reel
QFN24
(Pb-Free)
NB100LVEP91MNG 92 Units/Tube
For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
.
NB100LVEP91
www.onsemi.com
2
D1
D1
D2
Q0
Q1
Q1
V
EE
D0
Q0
D2
D0
V
CC
Figure 1. Logic Diagram
Q2
Q2
GND
V
BB
Positive Level
Input
NECL Output
R1
R1
R1
R1
R1
R1
R2
R2
R2
Table 1. PIN DESCRIPTION
Pin
Name I/O
Default
State
Description
SOIC QFN
1, 20 3, 4, 12 V
CC
Positive Supply Voltage. All V
CC
Pins must be Externally
Connected to Power Supply to Guarantee Proper Operation.
10 15, 16 V
EE
Negative Supply Voltage. All V
EE
Pins must be Externally
Connected to Power Supply to Guarantee Proper Operation.
14, 17 19, 20,
23, 24
GND Ground.
4, 7 7, 11 V
BB
ECL Reference Voltage Output
2, 5, 8 5, 8, 13 D[0:2] LVPECL, LVDS, LVTTL,
LVCMOS, CML, HSTL Input
Low
Non-inverted Differential Inputs [0:2]. Internal 75 kW to GND.
3, 6, 9 6, 9, 14 D[0:2] LVPECL, LVDS,
LVTTL,LVCMOS, CML,
HSTL Input
High
Inverted Differential Inputs [0:2]. Internal 75 kW to GND and
75 kW to V
CC
. When Inputs are Left Open They Default to
(V
CC
GND) / 2.
19,16,13 2, 22, 18 Q[0:2] LVNECL Output Non-inverted Differential Outputs [0:2]. Typically Terminated
with 50 W to V
TT
= V
CC
2 V
18,15,12 1, 21, 17 Q[0:2] LVNECL Output Inverted Differential Outputs [0:2]. Typically Terminated with
50 W to V
TT
= V
CC
2 V
11 10 NC No Connect. The NC Pin is NOT Electrically Connected to
the Die and may Safely be Connected to Any Voltage from
V
EE
to V
CC
.
N/A EP Exposed Pad. (Note 1)
1. The thermally conductive exposed pad on the package bottom (see case drawing) must be attached to a heat sinking conduit and may
only be electrically connected to V
EE
(not GND).
NB100LVEP91
www.onsemi.com
3
D1
D1 D2
1718 16 15 14 13 12
43
56789
Q0
11
10
Q1 Q1 Q2 Q2 NC
V
EE
D0
1920
21
V
CC
Q0
D0 D2V
CC
V
BB
NB100LVEP91
GNDGND
V
BB
Figure 2. SOIC20 WB Lead Pinout (Top View)*
V
EE
D2
GND
Q0
D1
V
CC
V
CC
GND GND Q1
V
BB
NCV
BB
V
CC
GNDQ1
D1
D2
Q2
V
EE
NB100LVEP91
Figure 3. QFN24 Lead Pinout (Top View)*
Q2
Q0
D0
D0
18
12
4
3
5
6
789 1110
2
1
17
16
15
14
13
1924 23 22 2021
Exposed Pad
(EP)
*All V
CC
, V
EE
and GND pins must be externally connected to
a power supply. The thermally conductive exposed pad on the
package bottom (see case drawing) must be attached to a suf-
ficient heat-sinking conduit and may only be electronically
connected to V
EE
(not GND).
*All V
CC
, V
EE
and GND pins must be externally connected to
a power supply.
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
(R1)
75 kW
Internal Input Pullup Resistor
(R2)
75 kW
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 150 V
> 2 kV
Moisture Sensitivity (Note 1) Pb-Free Pkg
SOIC20 WB
QFN24
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V0 @ 0.125 in
Transistor Count 446 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.

NB100LVEP91DWG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Translation - Voltage Levels 2.5V/3.3V Any LVL to -2.5V/-3.3V/-5V NECL
Lifecycle:
New from this manufacturer.
Delivery:
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