7
Switching Specifications (AC)
Over recommended operating conditions unless otherwise specified.
Test
Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note
Propagation Delay Time to t
PLH
0.1 0.2 0.7 µs Rg = 47 Ω, 10,11, 14
High Output Level Cg = 3 nF, 12,13,
Propagation Delay Time to t
PHL
0.1 0.3 0.7 µs
f = 10 kHz,
14,17
Low Output Level
Duty Cycle =
Propagation Delay PDD -0.5 0.5 µs
50%,
10
Difference Between Any
I
F =
8 mA,
Two Parts or Channels
V
CC
= 30 V
Rise Time t
R
50 ns
Fall Time t
F
50 ns
Output High Level Common
|CM
H
| 25 35 kV/µsT
A
= 25°C, 18 11
Mode Transient Immunity V
CM
= 1 kV
Output Low Level Common
|CM
L
| 25 35 kV/µs1812
Mode Transient Immunity
Package Characteristics
Test
Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note
Input-Output Momentary V
ISO
3750 V
rms
T
A
=25°C, 8,9
Withstand Voltage RH<50% for
Input-Output Resistance R
I-O
10
12
Ω V
I-O
=500 V 9
Input-Output Capacitance C
I-O
0.6 pF Freq=1 MHz
Notes:
1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with I
O
peak
minimum = 0.4 A. See Application section for additional details on limiting I
OL
peak.
3. Derate linearly above 85°C, free air temperature at the rate of 4.0 mW/°C.
4. Input power dissipation does not require derating.
5. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%.
6. In this test, V
OH
is measured with a DC load current. When driving capacitive load V
OH
will approach V
CC
as I
OH
approaches zero amps.
7. Maximum pulse width = 1 ms, maximum duty cycle = 20%.
8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V
rms
for 1 second (leakage detection
current limit I
I-O
≤ 5 µA). This test is performed before 100% production test for partial discharge (method B) shown in the IEC/EN/DIN EN
60747-5-2 Insulation Characteristics Table, if applicable.
9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together.
10. PDD is the difference between t
PHL
and t
PLH
between any two parts or channels under the same test conditions.
11. Common mode transient immunity in the high state is the maximum tolerable |dVcm/dt| of the common mode pulse V
CM
to assure that the output
will remain in the high state (i.e. Vo > 6.0 V).
12. Common mode transient immunity in a low state is the maximum tolerable |dV
CM
/dt| of the common mode pulse, V
CM
, to assure that the output
will remain in a low state (i.e. Vo < 1.0 V).
13. This load condition approximates the gate load of a 1200 V/25 A IGBT.
14. The power supply current increases when operating frequency and Qg of the driven IGBT increases.
