10
FN7306.7
August 25, 2010
Description of Operation and Application
Information
Product Description
The EL5175 and EL5375 are wide bandwidth, low power
and single/differential ended to single-ended output
amplifiers. The EL5175 is a single channel differential to
single-ended amplifier. The EL5375 is a triple channel
differential to single ended amplifier. The EL5175 and
EL5375 are internally compensated for closed loop gain of
+1 orgreater. Connected in gain of 1 and driving a 500Ω
load, the EL5175 and EL5375 have a -3dB bandwidth of
550MHz. Driving a 150Ω load at gain of 2, the bandwidth is
about 130MHz. The bandwidth at the REF input is about
450MHz. The EL5175 and EL5375 is available with a
power-down feature to reduce the power while the amplifier
is disabled.
Input, Output and Supply Voltage Range
The EL5175 and EL5375 have been designed to operate
with a single supply voltage of 5V to 10V or a split supplies
with its total voltage from 5V to 10V. The amplifiers have an
input common mode voltage range from -4.3V to 3.3V for
±5V supply. The differential mode input range (DMIR)
between the two inputs is approximately -2.3V to +2.3V. The
input voltage range at the REF pin is from -3.6V to 3.3V. If
the input common mode or differential mode signal is outside
the above-specified ranges, it will cause the output signal to
become distorted.
The output of the EL5175 and EL5375 can swing from -3.9V
to 3.5V at 500Ω load at ±5V supply. As the load resistance
becomes lower, the output swing is reduced respectively.
Overall Gain Settings
The gain setting for the EL5175 and EL5375 is similar to the
conventional operational amplifier. The output voltage is
equal to the difference of the inputs plus V
REF
and then
times the gain.
Choice of Feedback Resistor and Gain Bandwidth
Product
For applications that require a gain of +1, no feedback
resistor is required. Just short the OUT+ pin to FBP pin and
OUT- pin to FBN pin. For gains greater than +1, the
feedback resistor forms a pole with the parasitic capacitance
at the inverting input. As this pole becomes smaller, the
amplifier's phase margin is reduced. This causes ringing in
the time domain and peaking in the frequency domain.
Therefore, R
F
has some maximum value that should not be
exceeded for optimum performance. If a large value of R
F
must be used, a small capacitor in the few Pico farad range
in parallel with R
F
can help to reduce the ringing and
peaking at the expense of reducing the bandwidth.
The bandwidth of the EL5175 and EL5375 depends on the
load and the feedback network. R
F
and R
G
appear in
parallel with the load for gains other than +1. As this
combination gets smaller, the bandwidth falls off.
Consequently, R
F
also has a minimum value that should not
be exceeded for optimum bandwidth performance. For gain
of +1, R
F
= 0 is optimum. For the gains other than +1,
optimum response is obtained with R
F
between 500Ω to
1kΩ. For A
V
= 2 and R
F
= R
G
= 806Ω, the BW is about
190MHz and the frequency response is very flat.
The EL5175 and EL5375 have a gain bandwidth product of
200MHz. For gains 5, its bandwidth can be predicted by
using Equation 2:
Driving Capacitive Loads and Cables
The EL5175 and EL5375 can drive 15pF capacitance in
parallel with 500Ω load to ground with less than 4.5dB of
peaking at a gain of +1. If less peaking is desired in
applications, a small series resistor (usually between 5Ω to
50Ω) can be placed in series with each output to eliminate
most peaking. However, this will reduce the gain slightly. If
the gain setting is greater than 1, the gain resistor R
G
can
then be chosen to make up for any gain loss, which may be
created by the additional series resistor at the output.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
Disable/Power-Down
The EL5175 and EL5375 can be disabled and its outputs
placed in a high impedance state. The turn-off time is about
1.2µs and the turn-on time is about 80ns. When disabled,
the amplifier's supply current is reduced to 80µA for I
S
+ and
120µA for I
S
- typically, thereby effectively eliminating the
V
O
V(
IN
+V
IN
-V
REF
+ ) 1
R
F
R
G
--------
+
⎝⎠
⎜⎟
⎛⎞
×=
(EQ. 1)
-
+
-
+
Σ G/B V
O
EN
V
IN
+
V
IN
-
V
REF
FB
R
G
R
F
FIGURE 25.
Gain BW 200MHz=×
(EQ. 2)
EL5175, EL5375
11
FN7306.7
August 25, 2010
power consumption. The amplifier's power-down can be
controlled by standard CMOS signal levels at the ENABLE
pin. The applied logic signal is relative to the V
S
+ pin. Letting
the EN
pin float or applying a signal that is less than 1.5V
below V
S
+ will enable the amplifier. The amplifier will be
disabled when the signal at the EN
pin is above V
S
+ - 0.5V.
If a TTL signal is used to control the enabled/disabled
function, Figure 26 could be used to convert the TTL signal
to CMOS signal.
Output Drive Capability
The EL5175 and EL5375 have internal short circuit
protection. Its typical short circuit current is ±67mA. If the
output is shorted indefinitely, the power dissipation could
easily increase such that the part will be destroyed.
Maximum reliability is maintained if the output current never
exceeds ±60mA. This limit is set by the design of the internal
metal interconnections.
Power Dissipation
With the high output drive capability of the EL5175 and
EL5375, it is possible to exceed the +135°C absolute
maximum junction temperature under certain load current
conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if the load conditions or package types need to be
modified for the amplifier to remain in the safe operating
area.
The maximum power dissipation allowed in a package is
determined according to Equation 3:
•T
JMAX
= Maximum junction temperature
•T
AMAX
= Maximum ambient temperature
θ
JA
= Thermal resistance of the package
Assume the REF pin is tired to GND for V
S
= ±5V
application, the maximum power dissipation actually
produced by an IC is the total quiescent supply current times
the total power supply voltage, plus the power in the IC due
to the load, or:
For sourcing, see Equation 4:
For sinking, see Equation 5:
Where:
•V
S
= Total supply voltage
•I
SMAX
= Maximum quiescent supply current per channel
•V
OUT
= Maximum output voltage of the application
•R
LOAD
= Load resistance
•I
LOAD
= Load current
i = Number of channels
By setting the two PD
MAX
equations equal to each other, we
can solve the output current and R
LOAD
to avoid the device
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as short as possible. The power supply
pin must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the V
S
- pin is
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from V
S
+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the V
S
- pin becomes the negative
supply rail.
For good AC performance, parasitic capacitance should be
kept to a minimum. Use of wire-wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
1k
10k
5V
EN
CMOS/TTL
FIGURE 26. CONVERSION OF TTL SIGNAL TO CMOS SIGNAL
PD
MAX
T
JMAX
T
AMAX
Θ
JA
---------------------------------------------
=
(EQ. 3)
PD
MAX
V
S
I
SMAX
V
S
+( V
OUT
)
V
OUT
R
LOAD
--------------------
i××+×=
(EQ. 4)
PD
MAX
V
S
I
SMAX
V
OUT
( V
S
- ) I
LOAD
] i××+×[=
(EQ. 5)
EL5175, EL5375
12
FN7306.7
August 25, 2010
Typical Applications
As the signal is transmitted through a cable, the high
frequency signal will be attenuated. One way to compensate
this loss is to boost the high frequency gain at the receiver
side.
Level Shifter and Signal Summer
The EL5175 and EL5375 contains two pairs of differential
pair input stages. It makes the inputs all high impedance. To
take advantage of the two high impedance inputs, the
EL5175 and EL5375 can be used as a signal summer to add
two signals together. One signal can be applied to V
IN
+; the
second signal can be applied to REF and V
IN
- is ground.
The output is equal to Equation 6:
Also, the EL5175 and EL5375 can be used as a level shifter
by applying a level control signal to the REF input.
0Ω
V
FB
V
INB
V
REF
EL5175/
EL5375
EL5173,
EL5373
V
OUT
50
50
Z
O
= 100Ω
V
IN
50Ω
50Ω
FIGURE 27. TWISTED PAIR CABLE RECEIVER
R
2
V
FB
V
INB
V
REF
EL5175,
EL5375
V
OUT
V
IN
50Ω
50Ω
R
1
R
3
C
1
Z
O
= 100Ω
f
A
f
C
f
GAIN
(dB)
1 + R
2
/R
1
1 + R
2
/ (R
1
+ R
3
)
FIGURE 28. COMPENSATED LINE RECEIVER
V
O
V
IN
( +V
REF
) Gain×+=
(EQ. 6)
EL5175, EL5375

EL5175ISZ-T13

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Differential Amplifiers EL5175ISZ 500MHZCVR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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