AD8116
–6–
PIN FUNCTION DESCRIPTIONS
Pin Name Pin Numbers Pin Description
INxx 2, 4, 6, 8, 10, 12, 14, 16, 18, Analog Inputs; xx = Channel No. 00 thru 15.
20, 22, 24, 26, 28, 30, 32
DATA IN 37, 126 Serial Data Input, TTL Compatible.
CLK 36, 125 Serial Clock, TTL Compatible. Falling edge triggered.
DATA OUT 35, 124 Serial Data Out, TTL Compatible.
UPDATE 38, 123 Enable (Transparent) “Low.” Allows serial register to connect directly to switch
matrix. Data latched when “high.”
RESET 39, 122 Disable Outputs, Enable “Low.”
CE 40, 121 Chip Enable, Enable “Low.” Must be “low” to clock in & latch data.
OUTyy 65, 67, 69, 71, 73, 75, 77, 79, Analog Outputs yy = Channel Nos. 00 thru 15.
81, 83, 85, 87, 89, 91, 93, 95
AGND 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, Analog Ground for inputs and switch matrix.
21, 23, 25, 27, 29, 31, 33, 128
DVCC 34, 127 +5 V for Digital Circuitry.
DGND 41, 120 Ground for Digital Circuitry.
DVEE 42, 119 –5 V for Digital Circuitry.
AVEE 43, 44, 45, 116, 117, 118 –5 V for Inputs and Switch Matrix.
AVCC 46, 47, 48, 113, 114, 115 +5 V for Inputs and Switch Matrix.
AGNDxx 56–63, 97–104 Ground for Output Amp, xx = Output Channel Nos. 00 thru 15. Must be connected.
AVCC00 96 +5 V for Output Channel 00. Must be connected.
AVCC15 64 +5 V for Output Channel 15. Must be connected.
AVCCxx/yy 68, 72, 76, 80, 84, 88, 92 +5 V for Output Amplifier that is shared by Channel Nos. xx and yy. Must be connected.
AVEExx/yy 66, 70, 74, 78, 82, 86, 90, 94 –5 V for Output Amplifier that is shared by Channel Nos. xx and yy. Must be connected.
Figure 5. I/O Pin Schematics
ESD
ESD
INPUT
V
CC
V
EE
a. Analog Input
ESD
ESD
OUTPUT
V
CC
V
EE
b. Analog Output
ESD
ESD
RESET
V
CC
20k⍀
c. Reset Input
ESD
ESD
INPUT
V
CC
V
EE
d. Logic Input
ESD
ESD
OUTPUT
V
CC
V
EE
2k⍀
e. Logic Output
REV. C
