14
QT113B [DATASHEET]
9525D–AT42–05/2013
4. Circuit Guidelines
4.1 Sample capacitor
Charge sampler C
S
can be virtually any plastic film or medium-K ceramic capacitor. The acceptable C
S
range is from
10 nF to 500 nF depending on the sensitivity required; larger values of C
S
demand higher stability to ensure reliable
sensing. Acceptable capacitor types include PPS film, polypropylene film, NPO/C0G ceramic, and X7R ceramic.
4.2 Option Strapping
The option pins OPT1 and OPT2 should never be left floating. If they are floated, the device will draw excess power
and the options will not be properly read on power-up. Intentionally, there are no pull-up resistors on these lines,
since pull-up resistors add to power drain if tied low.
The Gain input should be connected to either Vdd or Gnd.
Table 2-1 on page 7 and Table 3-1 on page 10 show the option strap configurations available.
4.3 Power Supply, PCB Layout
The power supply can range from 2.5 V to 5.0 V. At 3 V, current drain averages less than 600 µA in most cases, but
can be higher if C
S
is large. Increasing C
X
values will actually decrease power drain. Operation can be from batteries,
but be cautious about loads causing supply droop (see “Output Drive” on page 13).
As battery voltage sags with use or fluctuates slowly with temperature, the QT113B will track and compensate for
these changes automatically with only minor changes in sensitivity.
If the power supply is shared with another electronic system, care should be taken to assure that the supply is free of
digital spikes, sags, and surges which can adversely affect the QT113B. The QT113B will track slow changes in Vdd,
but it can be affected by rapid voltage steps.
if desired, the supply can be regulated using a conventional low current regulator, for example CMOS regulators that
have low quiescent currents. Bear in mind that such regulators generally have very poor transient line and load
stability; in some cases, shunting Vdd to Vss with a 4.7 k resistor to induce a continuous current drain can have a
very positive effect on regulator performance.
Parts placement: The chip should be placed to minimize the SNS2 trace length to reduce low frequency pickup, and
to reduce stray C
X
which degrades gain. The C
S
and R
series
resistors (see Figure 1-1 on page 3) should be placed as
close to the body of the chip as possible so that the SNS2 trace between R
series
and the SNS2 pin is very short,
thereby reducing the antenna-like ability of this trace to pick up high frequency signals and feed them directly into the
chip.
For best EMC performance the circuit should be made entirely with SMT components.
SNS trace routing: Keep the SNS2 electrode trace (and the electrode itself) away from other signal, power, and
ground traces including over or next to ground planes. Adjacent switching signals can induce noise onto the sensing
signal; any adjacent trace or ground plane next to or under either SNS trace will cause an increase in C
X
load and
desensitize the device.
For proper operation a 100 nF ceramic bypass capacitor must be used directly between Vdd and Vss; the bypass
cap should be placed very close to the device power pins.
