Philips Semiconductors
P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
Product data Rev. 05 — 17 December 2004 28 of 53
9397 750 14465
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
The P89LPC901 supports 6 interrupt sources: timers 0 and 1, brownout detect,
Watchdog/real-time clock, keyboard, and the comparator.
The P89LPC902 supports 6 interrupt sources: timers 0 and 1, brownout detect,
Watchdog/real-time clock, keyboard, and comparators 1 and 2.
The P89LPC903 supports 9 interrupt sources: timers 0 and 1, serial port Tx, serial
port Rx, combined serial port Rx/Tx, brownout detect, Watchdog/real-time clock,
keyboard, and comparators 1 and 2.
Each interrupt source can be individually enabled or disabled by setting or clearing a
bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a
global disable bit, EA, which disables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt,
but not by another interrupt of the same or lower priority. The highest priority interrupt
service cannot be interrupted by any other interrupt source. If two requests of
different priority levels are pending at the start of an instruction, the request of higher
priority level is serviced.
If requests of the same priority level are pending at the start of an instruction, an
internal polling sequence determines which request is serviced. This is called the
arbitration ranking. Note that the arbitration ranking is only used to resolve pending
requests of the same priority level.
8.11.1 External interrupt inputs
The P89LPC901/902/903 has a Keypad Interrupt function. This can be used as an
external interrupt input.
If enabled when the P89LPC901/902/903 is put into Power-down or Idle mode, the
interrupt will cause the processor to wake-up and resume operation. Refer to Section
8.14 “Power reduction modes” for details.
