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XC95144-7PQ100C

P1-P3P4-P6P7-P9P10-P10
DS067 (v5.7) May 28, 2009 www.xilinx.com
Product Specification 1
© 2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries.
All other trademarks are the property of their respective owners.
Features
• 7.5 ns pin-to-pin logic delays on all pins
•f
CNT
to 111 MHz
• 144 macrocells with 3,200 usable gates
• Up to 133 user I/O pins
• 5V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block (FB)
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables,
set and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design
protection
• High-drive 24 mA outputs
• 3.3V or 5V I/O capability
• Advanced CMOS 5V FastFLASH technology
• Supports parallel programming of more than one
XC9500 concurrently
• Available in 100-pin PQFP, 100-pin TQFP, and 160-pin
PQFP packages
Description
The XC95144 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC95144 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
CC
(mA) = MC
HP
(1.7) + MC
LP
(0.9) + MC (0.006 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95144
device.
0
XC95144 In-System
Programmable CPLD
DS067 (v5.7) May 28, 2009
05
Product Specification
R
Figure 1: Typical I
CC
vs. Frequency for XC95144
Clock Frequency (MHz)
Typical I
CC
(mA)
050
200
(480)
(320)
400
600
100
High Performance
Low Power
DS067_01_110101
(160)
(300)
XC95144 In-System Programmable CPLD
DS067 (v5.7) May 28, 2009 www.xilinx.com
Product Specification 2
R
Figure 2: XC95144 Architecture
Function block outputs (indicated by the bold line) drive the I/O blocks directly.
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port
3
36
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
2
1
I/O
I/O
I/O
I/O
3
DS067_02_110101
1
Function
Block 2
36
18
18
Function
Block 3
Macrocells
1 to 18
Macrocells
1 to 18
36
Function
Block 8
36
18
18
Function
Block 4
Macrocells
1 to 18
36
18
Fast CONNECT II Switch Matrix
XC95144 In-System Programmable CPLD
DS067 (v5.7) May 28, 2009 www.xilinx.com
Product Specification 3
R
Absolute Maximum Ratings
Recommended Operation Conditions
Quality and Reliability Characteristics
DC Characteristic Over Recommended Operating Conditions
Symbol Description Value Units
V
CC
Supply voltage relative to GND –0.5 to 7.0 V
V
IN
Input voltage relative to GND –0.5 to V
CC
+ 0.5 V
V
TS
Voltage applied to 3-state output –0.5 to V
CC
+ 0.5 V
T
STG
Storage temperature (ambient) –65 to +150
o
C
T
J
Junction temperature +150
o
C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Symbol Parameter Min Max Units
V
CCINT
Supply voltage for internal logic
and input buffers
Commercial T
A
= 0
o
C to 70
o
C 4.75 5.25 V
Industrial T
A
= –40
o
C to +85
o
C4.5 5.5
V
CCIO
Supply voltage for output drivers
for 5V operation
Commercial T
A
= 0
o
C to 70
o
C 4.75 5.25 V
Industrial T
A
= –40
o
C to +85
o
C4.5 5.5
Supply voltage for output drivers for 3.3V operation 3.0 3.6
V
IL
Low-level input voltage 0 0.80 V
V
IH
High-level input voltage 2.0 V
CCINT
+ 0.5 V
V
O
Output voltage 0 V
CCIO
V
Symbol Parameter Min Max Units
T
DR
Data Retention 20 - Years
N
PE
Program/Erase Cycles (Endurance) 10,000 - Cycles
Symbol Parameter Test Conditions Min Max Units
V
OH
Output high voltage for 5V outputs I
OH
= –4.0 mA, V
CC
= Min 2.4 - V
Output high voltage for 3.3V outputs I
OH
= –3.2 mA, V
CC
= Min 2.4 - V
V
OL
Output low voltage for 5V outputs I
OL
= 24 mA, V
CC
= Min - 0.5 V
Output low voltage for 3.3V outputs I
OL
= 10 mA, V
CC
= Min - 0.4 V
I
IL
Input leakage current V
CC
= Max
V
IN
= GND or V
CC
-±10μA
I
IH
I/O high-Z leakage current V
CC
= Max
V
IN
= GND or V
CC
-±10μA
C
IN
I/O capacitance V
IN
= GND
f = 1.0 MHz
-10pF
I
CC
Operating supply current
(low power mode, active)
V
I
= GND, No load
f = 1.0 MHz
160 (Typical) mA
P1-P3P4-P6P7-P9P10-P10

XC95144-7PQ100C

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