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XC95144-7PQ100C

P1-P3P4-P6P7-P9P10-P10
XC95144 In-System Programmable CPLD
DS067 (v5.7) May 28, 2009 www.xilinx.com
Product Specification 4
R
AC Characteristics
Symbol Parameter
XC95144-7 XC95144-10 XC95144-15
UnitsMin Max Min Max Min Max
T
PD
I/O to output valid - 7.5 - 10.0 - 15.0 ns
T
SU
I/O setup time before GCK 4.5 - 6.0 - 8.0 - ns
T
H
I/O hold time after GCK 0 - 0 - 0 - ns
T
CO
GCK to output valid - 4.5 - 6.0 - 8.0 ns
f
CNT
(1)
16-bit counter frequency 125.0 - 111.1 - 95.2 - MHz
f
SYSTEM
(2)
Multiple FB internal operating frequency 83.3 - 66.7 - 55.6 - MHz
T
PSU
I/O setup time before p-term clock input 0.5 - 2.0 - 4.0 - ns
T
PH
I/O hold time after p-term clock input 4.0 - 4.0 - 4.0 - ns
T
PCO
P-term clock output valid - 8.5 - 10.0 - 12.0 ns
T
OE
GTS to output valid - 5.5 - 6.0 - 11.0 ns
T
OD
GTS to output disable - 5.5 - 6.0 - 11.0 ns
T
POE
Product term OE to output enabled - 9.5 - 10.0 - 14.0 ns
T
POD
Product term OE to output disabled - 9.5 - 10.0 - 14.0 ns
T
WLH
GCK pulse width (High or Low) 4.0 - 4.5 - 5.5 - ns
T
APRPW
Asynchronous preset/reset pulse width
(High or Low)
7.0 - 7.5 - 8.0 - ns
Notes:
1. f
CNT
is the fastest 16-bit counter frequency available, using the local feedback when applicable.
f
CNT
is also the Export Control Maximum flip-flop toggle rate, f
TOG
.
2. f
SYSTEM
is the internal operating frequency for general purpose system designs spanning multiple FBs.
Figure 3: AC Load Circuit
Device Output
Output Type V
TEST
5.0V
3.3V
V
TEST
R
1
160Ω
260Ω
R
1
R
2
C
L
R
2
120Ω
360Ω
C
L
35 pF
35 pF
DS067_03_110101
V
CCIO
5.0V
3.3V
XC95144 In-System Programmable CPLD
DS067 (v5.7) May 28, 2009 www.xilinx.com
Product Specification 5
R
Internal Timing Parameters
Symbol Parameter
XC95144-7 XC95144-10 XC95144-15
UnitsMin Max Min Max Min Max
Buffer Delays
T
IN
Input buffer delay - 2.5 - 3.5 - 4.5 ns
T
GCK
GCK buffer delay - 1.5 - 2.5 - 3.0 ns
T
GSR
GSR buffer delay - 4.5 - 6.0 - 7.5 ns
T
GTS
GTS buffer delay - 5.5 - 6.0 - 11.0 ns
T
OUT
Output buffer delay - 2.5 - 3.0 - 4.5 ns
T
EN
Output buffer enable/disable delay - 0 - 0 - 0 ns
Product Term Control Delays
T
PTCK
Product term clock delay - 3.0 - 3.0 - 2.5 ns
T
PTSR
Product term set/reset delay - 2.0 - 2.5 - 3.0 ns
T
PTTS
Product term 3-state delay - 4.5 - 3.5 - 5.0 ns
Internal Register and Combinatorial Delays
T
PDI
Combinatorial logic propagation delay - 0.5 - 1.0 - 3.0 ns
T
SUI
Register setup time 1.5 - 2.5 - 3.5 - ns
T
HI
Register hold time 3.0 - 3.5 - 4.5 - ns
T
COI
Register clock to output valid time - 0.5 - 0.5 - 0.5 ns
T
AOI
Register async. S/R to output delay - 6.5 - 7.0 - 8.0 ns
T
RAI
Register async. S/R recover before clock 7.5 - 10.0 - 10.0 - ns
T
LOGI
Internal logic delay - 2.0 - 2.5 - 3.0 ns
T
LOGILP
Internal low power logic delay - 10.0 - 11.0 - 11.5 ns
Feedback Delays
T
F
FastCONNECT feedback delay - 8.0 - 9.5 - 11.0 ns
T
LF
Function block local feedback delay - 4.0 - 3.5 - 3.5 ns
Time Adders
T
PTA
(1)
Incremental product term allocator delay - 1.0 - 1.0 - 1.0 ns
T
SLEW
Slew-rate limited delay - 4.0 - 4.5 - 5.0 ns
Notes:
1. T
PTA
is multiplied by the span of the function as defined in the XC9500 family data sheet.
XC95144 In-System Programmable CPLD
DS067 (v5.7) May 28, 2009 www.xilinx.com
Product Specification 6
R
XC95144 I/O Pins
Function
Block
Macro-
cell TQ100 PQ100 PQ160
BScan
Order
Function
Block
Macro-
cell TQ100 PQ100 PQ160
BScan
Order
1 1 – – 25 429 3 1 – – 43 321
1 2 11 13 18 426 3 2 23
[1]
25
[1]
35
[1]
318
[1]
1 3 12 14 19 423 3 3 – – 45 315
1 4 – – 27 420 3 4 – – 48 312
1 5 13 15 21 417 3 5 24 26 36 309
1 6 14 16 22 414 3 6 25 27 37 306
1 7 – – 32 411 3 7 – – 50 303
1 8 15 17 23 408 3 8 27
[1]
29
[1]
42
[1]
300
[1]
1 9 16 18 24 405 3 9 28 30 44 297
1 10 – – 34 402 3 10 – – 52 294
1 11 17 19 26 399 3 11 29 31 47 291
1 12 18 20 28 396 3 12 30 32 49 288
1 13 – – 38 393 3 13 – – 53 285
1 14 19 21 29 390 3 14 32 34 54 282
1 15 20 22 30 387 3 15 33 35 56 279
1 16 – – 39 384 3 16 – – 55 276
11722
[1]
24
[1]
33
[1]
381
[1]
3 17 34 36 57 273
1 18 – – – 378 3 18 – – – 270
2 1 – – 158 375 4 1 – – 132 267
2299
[1]
1
[1]
159
[1]
372
[1]
4 2 87 89 140 264
2 3 – – 3 369 4 3 – – 147 261
2 4 – – 5 366 4 4 – – 149 258
251
[1]
3
[1]
2
[1]
363
[1]
4 5 89 91 142 255
262
[1]
4
[1]
4
[1]
360
[1]
4 6 90 92 143 252
2 7 – – 7 357 4 7 – – 150 249
283
[1]
5
[1]
6
[1]
354
[1]
4 8 91 93 144 246
294
[1]
6
[1]
8
[1]
351
[1]
4 9 92 94 145 243
2 10 – – 9 348 4 10 – – 151 240
2 11 6 8 11 345 4 11 93 95 146 237
2 12 7 9 12 342 4 12 94 96 148 234
2 13 – – 14 339 4 13 – – 153 231
2 14 8 10 13 336 4 14 95 97 152 228
2 15 9 11 15 333 4 15 96 98 154 225
2 16 – – 16 330 4 16 – – 155 222
2 17 10 12 17 327 4 17 97 99 156 219
2 18 – – – 324 4 18 – – – 216
Notes:
1. Global control pin.
Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG, and Global Signals are
fixed.
P1-P3P4-P6P7-P9P10-P10

XC95144-7PQ100C

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