Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. D1
3/10/2015
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS62WV25616DALL/DBLL, IS65WV25616DBLL
256K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC SRAM
FEATURES
• High-speed access time: 35, 45, 55 ns
• CMOSlowpoweroperation
30 mW (typical) operating
6µW(typical)CMOSstandby
• TTLcompatibleinterfacelevels
• Singlepowersupply
1.65V--2.2V V
dd (IS62WV25616DALL)
2.3V--3.6V V
dd (IS62/65WV25616DBLL)
• Fullystaticoperation:noclockorrefresh
required
• Threestateoutputs
• Datacontrolforupperandlowerbytes
• IndustrialandAutomotivetemperaturesupport
• Lead-freeavailable
• 2CSoptionavailable
DESCRIPTION
TheISSIIS62WV25616DALLandIS62/65WV25616DBLL
arehigh-speed,lowpower,4MbitSRAMsorganizedas
256K words by 16 bits. It is fabricated using ISSI's high-
performanceCMOStechnology.Thishighlyreliableprocess
coupled with innovative circuit design techniques, yields
high-performance and low power consumption devices.
When CS1 is HIGH (deselected) or when CS2 is LOW
(deselcted) or when CS1isLOW,CS2isHIGHandboth
LB and UB are HIGH, the device assumes a standby mode
at which the power dissipation can be reduced down with
CMOSinputlevels.
Easy memory expansion is provided by using Chip Enable
andOutputEnableinputs.TheactiveLOWWriteEnable(WE)
controls both writing and reading of the memory. A data byte
allows Upper Byte (UB)andLowerByte(LB) access.
TheIS62WV25616DALLandIS62/65WV25616DBLLare
packaged in the JEDEC standard 44-PinTSOP(TYPEII)
and 48-pin mini BGA (6mmx8mm).
FUNCTIONAL BLOCK DIAGRAM
MARCH 2015
A0-A17
CS1
CS2
OE
WE
256K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
IS62WV25616DALL/DBLL, IS65WV25616DBLL
2 Integrated Silicon Solution, Inc. — www.issi.com
Rev. D1
3/10/2015
PIN DESCRIPTIONS
A0-A17 Address Inputs
I/O0-I/O15 DataInputs/Outputs
CS1, CS2 Chip Enable Input
OE OutputEnableInput
WE Write Enable Input
LB Lower-byteControl(I/O0-I/O7)
UB Upper-byteControl(I/O8-I/O15)
NC No Connection
Vdd Power
GND Ground
44-Pin mini TSOP (Type II)
(Package Code T)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CS1
I/O0
I/O1
I/O2
I/O3
V
DD
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
V
DD
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A17
PIN CONFIGURATIONS
48- ball mini BGA (6mm x 8mm)
(Package Code B)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB
OE
A0
A1
A2
NC
I/O
8
UB A3
A4
CSI I/O
0
I/O
9
I/O
10
A5
A6
I/O
1
I/O
2
GND
I/O
11
A17
A7
I/O
3
VDD
VDD
I/O
12
NC
A16
I/O
4
GND
I/O
14
I/O
13
A14
A15
I/O
5
I/O
6
I/O
15
NC
A12
A13
WE
I/O
7
NC
A8
A9
A10
A11 NC
48-Pin mini BGA (6mm x 8mm)*
2 CS Option (Package Code B2)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB
OE
A0
A1
A2
CS2
I/O
8
UB A3
A4
CS1 I/O
0
I/O
9
I/O
10
A5
A6
I/O
1
I/O
2
GND
I/O
11
A17
A7
I/O
3
VDD
VDD
I/O
12
NC
A16
I/O
4
GND
I/O
14
I/O
13
A14
A15
I/O
5
I/O
6
I/O
15
NC
A12
A13
WE
I/O
7
NC
A8
A9
A10
A11 NC
*Available upon request
Integrated Silicon Solution, Inc. — www.issi.com 3
Rev. D1
3/10/2015
IS62WV25616DALL/DBLL, IS65WV25616DBLL
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
Vterm TerminalVoltagewithRespecttoGND –0.5toVdd + 0.5 V
Vdd VddRelatestoGND –0.3to4.0 V
tstg StorageTemperature –65to+150 °C
Pt Power Dissipation 1.0 W
Notes:
1.StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycausepermanentdamageto
thedevice.Thisisastressratingonlyandfunctionaloperationofthedeviceattheseoranyotherconditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
(1,2)
Symbol Parameter Conditions Max. Unit
Cin Input Capacitance Vin = 0V 6 pF
C
i/O
Input/OutputCapacitance VOut = 0V 8 pF
Notes:
1.Testedinitiallyandafteranydesignorprocesschangesthatmayaffecttheseparameters.
2. Testconditions:T
a = 25°C, f=1MHz,Vdd = 3.3V.
TRUTH TABLE
I/O PIN
Mode WE CS1 CS2 OE LB UB I/O0-I/O7 I/O8-I/O15 VDD Current
NotSelected X H X X X X High-Z High-Z isb1, isb2
X X L X X X High-Z High-Z isb1, isb2
X X X X H H High-Z High-Z isb1, isb2
OutputDisabled H L H H L X High-Z High-Z iCC
H L H H X L High-Z High-Z iCC
Read H L H L L H dOut High-Z iCC
H L H L H L High-Z dOut
H L H L L L dOut dOut
Write L L H X L H din High-Z iCC
L L H X H L High-Z din
L L H X L L din din

IS62WV25616DBLL-45TI

Mfr. #:
Manufacturer:
Description:
IC SRAM 4M PARALLEL 44TSOP2
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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