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IS62WV25616DBLL-45TI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
IS62WV25616DALL/DBLL, IS65WV25616DBLL
10 Integrated Silicon Solution, Inc. — www.issi.com
Rev. D1
3/10/2015
AC WAVEFORMS
WRITE CYCLE NO. 1
(1,2)
(CS1 Controlled, OE=HIGHorLOW)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CS1
CS2
WE
DOUT
DIN
LB, UB
t
PWB
Notes:
1. WRITEisaninternallygeneratedsignalassertedduringanoverlapoftheLOWstatesontheCS1 , CS2 and WE inputs and at
least one of the LB and UBinputsbeingintheLOWstate.
2. WRITE=(CS1) [ (LB) = (UB) ] (WE).
Integrated Silicon Solution, Inc. — www.issi.com 11
Rev. D1
3/10/2015
IS62WV25616DALL/DBLL, IS65WV25616DBLL
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CS1
CS2
WE
LB, UB
DOUT
DIN
AC WAVEFORMS
WRITE CYCLE NO. 2
(WE Controlled: OE is HIGH During Write Cycle)
IS62WV25616DALL/DBLL, IS65WV25616DBLL
12 Integrated Silicon Solution, Inc. — www.issi.com
Rev. D1
3/10/2015
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CS1
CS2
WE
LB, UB
DOUT
DIN
AC WAVEFORMS
WRITE CYCLE NO. 3
(WE Controlled: OEisLOWDuringWriteCycle)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

IS62WV25616DBLL-45TI

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IC SRAM 4M PARALLEL 44TSOP2
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