LPC2420_60 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6.2 — 16 October 2013 22 of 87
NXP Semiconductors
LPC2420/2460
Flashless 16-bit/32-bit microcontroller
P3[31]/D31/
MAT1[2]
25
[1]
J3
[1]
I/O P3[31] — General purpose digital input/output pin.
I/O D31 — External memory data line 31.
O MAT1[2] — Match output for Timer 1, channel 2.
P4[0] to P4[31] I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for
each bit. The operation of port 4 pins depends upon the pin function
selected via the Pin Connect block.
P4[0]/A0 75
[1]
U9
[1]
I/O P4[0] — ]General purpose digital input/output pin.
I/O A0 — External memory address line 0.
P4[1]/A1 79
[1]
U10
[1]
I/O P4[1] — General purpose digital input/output pin.
I/O A1 — External memory address line 1.
P4[2]/A2 83
[1]
T11
[1]
I/O P4[2] — General purpose digital input/output pin.
I/O A2 — External memory address line 2.
P4[3]/A3 97
[1]
U16
[1]
I/O P4[3] — General purpose digital input/output pin.
I/O A3 — External memory address line 3.
P4[4]/A4 103
[1]
R15
[1]
I/O P4[4] — General purpose digital input/output pin.
I/O A4 — External memory address line 4.
P4[5]/A5 107
[1]
R16
[1]
I/O P4[5] — General purpose digital input/output pin.
I/O A5 — External memory address line 5.
P4[6]/A6 113
[1]
M14
[1]
I/O P4[6] — General purpose digital input/output pin.
I/O A6 — External memory address line 6.
P4[7]/A7 121
[1]
L16
[1]
I/O P4[7] — General purpose digital input/output pin.
I/O A7 — External memory address line 7.
P4[8]/A8 127
[1]
J17
[1]
I/O P4[8] — General purpose digital input/output pin.
I/O A8 — External memory address line 8.
P4[9]/A9 131
[1]
H17
[1]
I/O P4[9] — General purpose digital input/output pin.
I/O A9 — External memory address line 9.
P4[10]/A10 135
[1]
G17
[1]
I/O P4[10] — General purpose digital input/output pin.
I/O A10 — External memory address line 10.
P4[11]/A11 145
[1]
F14
[1]
I/O P4[11] — General purpose digital input/output pin.
I/O A11 — External memory address line 11.
P4[12]/A12 149
[1]
C16
[1]
I/O P4[12] — General purpose digital input/output pin.
I/O A12 — External memory address line 12.
P4[13]/A13 155
[1]
B16
[1]
I/O P4[13] — General purpose digital input/output pin.
I/O A13 — External memory address line 13.
P4[14]/A14 159
[1]
B15
[1]
I/O P4[14] — General purpose digital input/output pin.
I/O A14 — External memory address line 14.
P4[15]/A15 173
[1]
A11
[1]
I/O P4[15] — General purpose digital input/output pin.
I/O A15 — External memory address line 15.
P4[16]/A16 101
[1]
U17
[1]
I/O P4[16] — General purpose digital input/output pin.
I/O A16 — External memory address line 16.
Table 4. Pin description …continued
Symbol Pin Ball Type Description
LPC2420_60 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6.2 — 16 October 2013 23 of 87
NXP Semiconductors
LPC2420/2460
Flashless 16-bit/32-bit microcontroller
P4[17]/A17 104
[1]
P14
[1]
I/O P4[17] — General purpose digital input/output pin.
I/O A17 — External memory address line 17.
P4[18]/A18 105
[1]
P15
[1]
I/O P4[18] — General purpose digital input/output pin.
I/O A18 — External memory address line 18.
P4[19]/A19 111
[1]
P16
[1]
I/O P4[19] — General purpose digital input/output pin.
I/O A19 — External memory address line 19.
P4[20]/A20/
SDA2/SCK1
109
[1]
R17
[1]
I/O P4[20] — General purpose digital input/output pin.
I/O A20 — External memory address line 20.
I/O SDA2 — I
2
C2 data input/output (this is not an open-drain pin).
I/O SCK1 — Serial Clock for SSP1.
P4[21]/A21/
SCL2/SSEL1
115
[1]
M15
[1]
I/O P4[21] — General purpose digital input/output pin.
I/O A21 — External memory address line 21.
I/O SCL2 — I
2
C2 clock input/output (this is not an open-drain pin).
I/O SSEL1 — Slave Select for SSP1.
P4[22]/A22/
TXD2/MISO1
123
[1]
K14
[1]
I/O P4[22] — General purpose digital input/output pin.
I/O A22 — External memory address line 22.
O TXD2 — Transmitter output for UART2.
I/O MISO1 — Master In Slave Out for SSP1.
P4[23]/A23/
RXD2/MOSI1
129
[1]
J15
[1]
I/O P4[23] — General purpose digital input/output pin.
I/O A23 — External memory address line 23.
I RXD2 — Receiver input for UART2.
I/O MOSI1 — Master Out Slave In for SSP1.
P4[24]/OE
183
[1]
B8
[1]
I/O P4[24] — General purpose digital input/output pin.
O OE
LOW active Output Enable signal.
P4[25]/WE
179
[1]
B9
[1]
I/O P4[25] — General purpose digital input/output pin.
O WE
LOW active Write Enable signal.
P4[26]/BLS0
119
[1]
L15
[1]
I/O P4[26] — General purpose digital input/output pin.
O BLS0
LOW active Byte Lane select signal 0.
P4[27]/BLS1
139
[1]
G15
[1]
I/O P4[27] — General purpose digital input/output pin.
O BLS1
LOW active Byte Lane select signal 1.
P4[28]/BLS2
/
MAT2[0]/TXD3
170
[1]
C11
[1]
I/O P4 [28] — General purpose digital input/output pin.
O BLS2
LOW active Byte Lane select signal 2.
O MAT2[0] — Match output for Timer 2, channel 0.
O TXD3 — Transmitter output for UART3.
P4[29]/BLS3
/
MAT2[1]/RXD3
176
[1]
B10
[1]
I/O P4[29] — General purpose digital input/output pin.
O BLS3
LOW active Byte Lane select signal 3.
O MAT2[1] — Match output for Timer 2, channel 1.
I RXD3 — Receiver input for UART3.
P4[30]/CS0
187
[1]
B7
[1]
I/O P4[30] — General purpose digital input/output pin.
O CS0
LOW active Chip Select 0 signal.
Table 4. Pin description …continued
Symbol Pin Ball Type Description
LPC2420_60 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6.2 — 16 October 2013 24 of 87
NXP Semiconductors
LPC2420/2460
Flashless 16-bit/32-bit microcontroller
P4[31]/CS1 193
[1]
A4
[1]
I/O P4[31] — General purpose digital input/output pin.
O CS1
LOW active Chip Select 1 signal.
ALARM 37
[7]
N1
[7]
O ALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH
when a RTC alarm is generated.
USB_D252U1I/OUSB_D2 — USB port 2 bidirectional D line.
DBGEN 9
[1][8]
F4
[1][8]
I DBGEN — JTAG interface control signal. Also used for boundary
scanning.
TDO 2
[1][9]
D3
[1][9]
O TDO — Test data out for JTAG interface.
TDI 4
[1][8]
C2
[1][8]
I TDI — Test data in for JTAG interface.
TMS 6
[1][8]
E3
[1][8]
I TMS — Test Mode Select for JTAG interface.
TRST
8
[1][8]
D1
[1][8]
I TRSTTest Reset for JTAG interface.
TCK 10
[1][9]
E2
[1][9]
I TCK — Test Clock for JTAG interface. This clock must be slower than
1
6
of the CPU clock (CCLK) for the JTAG interface to operate.
RTCK 206
[1][8]
C3
[1][8]
I/O RTCK — JTAG interface control signal.
Note: LOW on this pin while RESET is LOW enables ETM pins
(P2[9:0]) to operate as Trace port after reset.
RSTOUT
29 K3 O RSTOUTThis is a 3.3 V pin. LOW on this pin indicates
LPC2420/2460 being in Reset state.
RESET
35
[10]
M2
[10]
I external reset input: A LOW on this pin resets the device, causing
I/O ports and peripherals to take on their default states, and processor
execution to begin at address 0. TTL with hysteresis, 5 V tolerant.
XTAL1 44
[7][11]
M4
[7][11]
I Input to the oscillator circuit and internal clock generator circuits.
XTAL2 46
[7][11]
N4
[7][11]
O Output from the oscillator amplifier.
RTCX1 34
[7][12]
K2
[7][12]
I Input to the RTC oscillator circuit.
RTCX2 36
[7][12]
L2
[7][12]
O Output from the RTC oscillator circuit.
V
SSIO
33, 63,
77, 93,
114,
133, 148,
169, 189,
200
[7]
L3, T5,
R9,
P12,
N16,
H14,
E15, A12,
B6, A2
[7]
I ground: 0 V reference for the digital I/O pins.
V
SSCORE
32, 84,
172
[7]
K4, P10,
D12
[7]
I ground: 0 V reference for the core.
V
SSA
22
[7]
J2
[7]
I analog ground: 0 V reference. This should nominally be the same
voltage as V
SSIO
/V
SSCORE
, but should be isolated to minimize noise
and error.
V
DD(3V3)
15, 60,
71, 89,
112,
125, 146,
165,
181,
198
[7]
G3,
P6, P8,
U13,
P17,
K16,
C17,
B13,
C9,
D7
[7]
I 3.3 V supply voltage: This is the power supply voltage for the I/O
ports.
n.c. 30, 117,
141
[7]
J4, L14,
G14
[7]
I not connected pins: These pins must be left unconnected (floating).
Table 4. Pin description
…continued
Symbol Pin Ball Type Description

LPC2460FET208,551

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU ARM7 USBHOST/ENET ROMLESS
Lifecycle:
New from this manufacturer.
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