10
FN9160.4
May 5, 2008
calculation in Equation 2 be used to ensure safe operation at
the desired frequency for the selected MOSFETs. The total
gate drive power losses due to the gate charge of MOSFETs
and the driver’s internal circuitry and their corresponding
average driver current can be estimated with Equations 2
and 3, respectively:
where the gate charge (Q
G1
and Q
G2
) is defined at a
particular gate to source voltage (V
GS1
and V
GS2
) in the
corresponding MOSFET datasheet; I
Q
is the driver’s total
quiescent current with no load at both drive outputs; N
Q1
and N
Q2
are number of upper and lower MOSFETs,
respectively; PVCC is the drive voltages for both upper and
lower FETs, respectively. The I
Q*
VCC product is the
quiescent power of the driver without capacitive load and is
typically 200mW at 300kHz.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R
G1
and R
G2
) and the internal gate resistors
(R
GI1
and R
GI2
) of MOSFETs. Figures 3 and 4 show the
typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated in Equation 4:
Layout Considerations
For heat spreading, place copper underneath the IC whether
it has an exposed pad or not. The copper area can be
extended beyond the bottom area of the IC and/or
connected to buried copper plane(s) with thermal vias. This
combination of vias for vertical heat escape, extended
copper plane, and buried planes for heat spreading allows
the IC to achieve its full thermal potential.
Place each channel power component as close to each
other as possible to reduce PCB copper losses and PCB
parasitics: shortest distance between DRAINs of upper FETs
and SOURCEs of lower FETs; shortest distance between
DRAINs of lower FETs and the power ground. Thus, smaller
amplitudes of positive and negative ringing are on the
switching edges of the PHASE node. However, some space
in between the power components is required for good
airflow. The traces from the drivers to the FETs should be
kept short and wide to reduce the inductance of the traces
and to promote clean drive signals.
P
Qg_TOT
2P
Qg_Q1
• 2P
Qg_Q2
• I
Q
VCC•++=
(EQ. 2)
P
Qg_Q1
Q
G1
PVCC
2
•
V
GS1
---------------------------------------
f
SW
• N
Q1
•=
P
Qg_Q2
Q
G2
PVCC
2
•
V
GS2
---------------------------------------
f
SW
• N
Q2
•=
I
DR
Q
G1
N
Q1
•
V
GS1
----------------------------- -
Q
G2
N
Q2
•
V
GS2
----------------------------- -
+
⎝⎠
⎜⎟
⎛⎞
f
SW
2• I
Q
+•=
(EQ. 3)
P
DR
2P•
DR_UP
2P•
DR_LOW
I
Q
VCC•++=
(EQ. 4)
P
DR_UP
R
HI1
R
HI1
R
EXT1
+
--------------------------------------
R
LO1
R
LO1
R
EXT1
+
----------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
P
Qg_Q1
2
---------------------
•=
P
DR_LOW
R
HI2
R
HI2
R
EXT2
+
--------------------------------------
R
LO2
R
LO2
R
EXT2
+
----------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
P
Qg_Q2
2
---------------------
•=
R
EXT1
R
G1
R
GI1
N
Q1
-------------
+=
R
EXT2
R
G2
R
GI2
N
Q2
-------------
+=
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Q1
D
S
G
R
GI1
R
G1
BOOT
R
HI1
C
DS
C
GS
C
GD
R
LO1
PHASE
PVCC
PVCC
Q2
D
S
G
R
GI2
R
G2
R
HI2
C
DS
C
GS
C
GD
R
LO2
ISL6614A
