ISL6614AIRZ Datasheet ISL6614ACBZ, ISL6614ACRZ, ISL6614ACRZ-T | P7-P9

FN9160.4

May 5, 2008

Functional Pin Description

PKG. PIN

NUMBER

SYMBOL FUNCTIONSOIC QFN

115 PWM1The PWM signal is the control input for the Channel 1 driver. The PWM signal can enter three distinct states during

operation, see “Three-State PWM Input” on page 8 for further details. Connect this pin to the PWM output of the

controller.

216 PWM2The PWM signal is the control input for the Channel 2 driver. The PWM signal can enter three distinct states during

operation, see “Three-State PWM Input” on page 8 for further details. Connect this pin to the PWM output of the

controller.

31 GNDBias and reference ground. All signals are referenced to this node.

4 2 LGATE1 Lower gate drive output of Channel 1. Connect to gate of the low-side power N-Channel MOSFET.

5 3 PVCC This pin supplies power to both the lower and higher gate drives in ISL6614A. Its operating range is +5V to 12V.

Place a high quality low ESR ceramic capacitor from this pin to GND.

64 PGNDIt is the power ground return of both low gate drivers.

- 5, 8 N/C No Connection.

7 6 LGATE2 Lower gate drive output of Channel 2. Connect to gate of the low-side power N-Channel MOSFET.

8 7 PHASE2 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 2. This

pin provides a return path for the upper gate drive.

9 9 UGATE2 Upper gate drive output of Channel 2. Connect to gate of high-side power N-Channel MOSFET.

10 10 BOOT2 Floating bootstrap supply pin for the upper gate drive of Channel 2. Connect the bootstrap capacitor between this

pin and the PHASE2 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal

Bootstrap Device” on page 9 for guidance in choosing the capacitor value.

11 11 BOOT1 Floating bootstrap supply pin for the upper gate drive of Channel 1. Connect the bootstrap capacitor between this

pin and the PHASE1 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal

Bootstrap Device” on page 9 for guidance in choosing the capacitor value.

12 12 UGATE1 Upper gate drive output of Channel 1. Connect to gate of high-side power N-Channel MOSFET.

13 13 PHASE1 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 1. This

pin provides a return path for the upper gate drive.

14 14 VCC Connect this pin to a +12V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR

ceramic capacitor from this pin to GND.

- 17 PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.

ISL6614A

FN9160.4

May 5, 2008

Description

Operation

Designed for versatility and speed, the ISL6614A MOSFET

driver controls both high-side and low-side N-Channel FETs of

two half-bridge power trains from two externally provided PWM

signals.

Prior to VCC exceeding its POR level, the Pre-POR

overvoltage protection function is activated during initial startup;

the upper gate (UGATE) is held low and the lower gate

(LGATE), controlled by the Pre-POR overvoltage protection

circuits, is connected to the PHASE. Once the VCC voltage

surpasses the VCC Rising Threshold (See “Electrical

Specifications” table on page 5), the PWM signal takes control

of gate transitions. A rising edge on PWM initiates the turn-off of

the lower MOSFET (see “TIMING DIAGRAM” on page 8). After

a short propagation delay [t

PDLL

], the lower gate begins to fall.

Typical fall times [t

] are provided in the “Electrical

Specifications” table on page 6. Adaptive shoot-through

circuitry monitors the PHASE voltage and determines the upper

gate delay time [t

PDHU

]. This prevents both the lower and

upper MOSFETs from conducting simultaneously. Once this

delay period is complete, the upper gate drive begins to rise

] and the upper MOSFET turns on.

A falling transition on PWM results in the turn-off of the upper

MOSFET and the turn-on of the lower MOSFET. A short

propagation delay [t

PDLU

] is encountered before the upper

gate begins to fall [t

]. Again, the adaptive shoot-through

circuitry determines the lower gate delay time, t

PDHL

. The

PHASE voltage and the UGATE voltage are monitored, and

the lower gate is allowed to rise after PHASE drops below a

level or the voltage of UGATE to PHASE reaches a level

depending upon the current direction (See the following

section for details). The lower gate then rises [t

], turning on

the lower MOSFET.

Advanced Adaptive Zero Shoot-Through Deadtime

Control (Patent Pending)

These drivers incorporate a unique adaptive deadtime control

technique to minimize deadtime, resulting in high efficiency

from the reduced freewheeling time of the lower MOSFETs’

body-diode conduction, and to prevent the upper and lower

MOSFETs from conducting simultaneously. This is

accomplished by ensuring either rising gate turns on its

MOSFET with minimum and sufficient delay after the other has

turned off.

During turn-off of the lower MOSFET, the PHASE voltage is

monitored until it reaches a -0.2V/+0.8V trip point for a

forward/reverse current, at which time the UGATE is released

to rise. An auto-zero comparator is used to correct the

DS(ON)

drop in the phase voltage preventing from false

detection of the -0.2V phase level during r

DS(ON)

conduction

period. In the case of zero current, the UGATE is released

after 35ns delay of the LGATE dropping below 0.5V. During

the phase detection, the disturbance of LGATE’s falling

transition on the PHASE node is blanked out to prevent falsely

tripping. Once the PHASE is high, the advanced adaptive

shoot-through circuitry monitors the PHASE and UGATE

voltages during a PWM falling edge and the subsequent

UGATE turn-off. If either the UGATE falls to less than 1.75V

above the PHASE or the PHASE falls to less than +0.8V, the

LGATE is released to turn on.

Three-State PWM Input

A unique feature of these drivers and other Intersil drivers is

the addition of a shutdown window to the PWM input. If the

PWM signal enters and remains within the shutdown window

for a set holdoff time, the driver outputs are disabled and

both MOSFET gates are pulled and held low. The shutdown

state is removed when the PWM signal moves outside the

shutdown window. Otherwise, the PWM rising and falling

thresholds outlined in the “Electrical Specifications” table on

PWM

UGATE

LGATE

PDHU

PDLL

TSSHD

PDTS

1.5V<PWM<3.2V

1.0V<PWM<2.6V

PDLU

PDHL

TSSHD

FIGURE 1. TIMING DIAGRAM

ISL6614A

FN9160.4

May 5, 2008

page 5 determine when the lower and upper gates are

enabled.

This feature helps prevent a negative transient on the output

voltage when the output is shut down, eliminating the

Schottky diode that is used in some systems for protecting

the load from reversed output voltage events.

In addition, more than 400mV hysteresis also incorporates

into the three-state shutdown window to eliminate PWM

input oscillations due to the capacitive load seen by the

PWM input through the body diode of the controller’s PWM

output when the power-up and/or power-down sequence of

bias supplies of the driver and PWM controller are required.

Power-On Reset (POR) Function

During initial startup, the VCC voltage rise is monitored.

Once the rising VCC voltage exceeds 9.8V (typically),

operation of the driver is enabled and the PWM input signal

takes control of the gate drives. If VCC drops below the

falling threshold of 7.6V (typically), operation of the driver is

disabled.

Pre-POR Overvoltage Protection

Prior to VCC exceeding its POR level, the upper gate is held

low and the lower gate is controlled by the overvoltage

protection circuits during initial startup. The PHASE is

connected to the gate of the low side MOSFET (LGATE),

which provides some protection to the microprocessor if the

upper MOSFET(s) is shorted during initial startup. For

complete protection, the low side MOSFET should have a

gate threshold well below the maximum voltage rating of the

load/microprocessor.

When VCC drops below its POR level, both gates pull low

and the Pre-POR overvoltage protection circuits are not

activated until VCC resets.

Internal Bootstrap Device

Both drivers feature an internal bootstrap Schottky diode.

Simply adding an external capacitor across the BOOT and

PHASE pins completes the bootstrap circuit. The bootstrap

function is also designed to prevent the bootstrap capacitor

from overcharging due to the large negative swing at the

trailing-edge of the PHASE node. This reduces voltage

stress on the boot to phase pins.

The bootstrap capacitor must have a maximum voltage

rating above UVCC + 5V and its capacitance value can be

chosen from Equation 1:

where Q

is the amount of gate charge per upper MOSFET

at V

GS1

gate-source voltage and N

is the number of control

MOSFETs per channel. The ΔV

BOOT_CAP

term is defined as

the allowable droop in the rail of the upper gate drive.

As an example, suppose two IRLR7821 FETs are chosen as

the upper MOSFETs. The gate charge, Q

, from the data

sheet is 10nC at 4.5V (V

) gate-source voltage. Then the

GATE

is calculated to be 53nC for PVCC = 12V. We will

assume a 200mV droop in drive voltage over the PWM

cycle. We find that a bootstrap capacitance of at least

0.267µF is required.

Gate Drive Voltage Versatility

The ISL6614A provides the user flexibility in choosing the

gate drive voltage for efficiency optimization. The ISL6614A

ties the upper and lower drive rails together. Simply applying

a voltage from 5V up to 12V on PVCC sets both gate drive

rail voltages simultaneously. Connecting a SOT-23 package

type of dual schottky diodes from the VCC to BOOT1 and

BOOT2 can bypass the internal bootstrap devices of both

upper gates so that the part can operate as a dual ISL6612

driver, which has a fixed VCC (12V typically) on the upper

gate and a programmable lower gate drive voltage.

Power Dissipation

Package power dissipation is mainly a function of the

switching frequency (f

), the output drive impedance, the

external gate resistance, and the selected MOSFET’s

internal gate resistance and total gate charge. Calculating

the power dissipation in the driver for a desired application is

critical to ensure safe operation. Exceeding the maximum

allowable power dissipation level will push the IC beyond the

maximum recommended operating junction temperature of

+125°C. The maximum allowable IC power dissipation for

the SO14 package is approximately 1W at room

temperature, while the power dissipation capacity in the

QFN packages, with an exposed heat escape pad, is around

2W. See “Layout Considerations” on page 10 for thermal

transfer improvement suggestions. When designing the

driver into an application, it is recommended that the

BOOT_CAP

GATE

ΔV

BOOT_CAP

--------------------------------------

≥

GATE

PVCC•

GS1

------------------------------------

•=

(EQ. 1)

50nC

20nC

FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

ΔV

BOOT_CAP

(V)

BOOT_CAP

(µF)

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0

GATE

= 100nC

ISL6614A

P1-P3 P4-P6 P7-P9 P10-P12

ISL6614AIRZ

Mfr. #:

Buy ISL6614AIRZ

Manufacturer:

Renesas / Intersil

Description:

Gate Drivers DL SYNCH BUCK MSFT HV DRVR DISABLE OTP

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New from this manufacturer.

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ISL6614AIRZ

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