10
voltage, the integrator capacitor voltage is raised or lowered
to compensate for the systematic offset at the error amplifier.
Compensation is limited to ±5% to minimize transient
overshoot when the device goes out of dropout, current limit,
or thermal shutdown.
Shutdown
Driving the EN_LDO pin low will put LDO1 and LDO2 into
the shutdown mode. Driving the EN_PWM pin low will put
the PWM into shutdown mode. Pulling the EN_PWM and
EN_LDO both pins low simultaneously, puts the complete
chip into shutdown mode, and supply current drops to 15µA
typical.
Protection Features for the LDOs
Current Limit
The ISL6413 monitors and controls the pass transistor’s
gate voltage to limit the output current. The current limit for
LDO1 is 330mA and LDO2 is 250mA. The output can be
shorted to ground without damaging the part due to the
current limit and thermal protection features.
Thermal Overload Protection
Thermal overload protection limits total power dissipation in
the ISL6413. When the junction temperature (T
J
) exceeds
+150°C, the thermal sensor sends a signal to the shutdown
logic, turning off the pass transistor and allowing the IC to
cool. The pass transistor turns on again after the IC’s
junction temperature typically cools by 20°C, resulting in a
pulsed output during continuous thermal overload
conditions. Thermal overload protection protects the
ISL6413 against fault conditions. For continuous operation,
do not exceed the absolute maximum junction temperature
rating of +150°C.
Operating Region and Power Dissipation
The maximum power dissipation of ISL6413 depends on the
thermal resistance of the IC package and circuit board, the
temperature difference between the die junction and ambient
air, and the rate of air flow. The power dissipated in the
device is:
PT = P1 + P2 + P3, where
P1 = I
OUT1
x V
OUT1
/I
IN
x V
IN
P2 = I
OUT2
(V
IN
– V
OUT2
)
P3 = I
OUT3
(V
IN
- V
OUT3
)
The maximum power dissipation is:
Pmax = (Tjmax – T
A
)/θJA
Where Tjmax = 150
o
C, T
A
= ambient temperature, and θJA
is the thermal resistance from the junction to the surrounding
environment.
The ISL6413 package features an exposed thermal pad on
its underside. This pad lowers the thermal resistance of the
package by providing a direct heat conduction path from the
die to the PC board. Additionally, the ISL6413’s ground
(GND_LDO and PGND) performs the dual function of
providing an electrical connection to system ground and
channeling heat away. Connect the exposed backside pad
direct to the GND_LDO ground plane.
Applications Information
LDO Regulator Capacitor Selection and Regulator
Stability
Capacitors are required at the ISL6413 LDO Regulators’
input and output for stable operation over the entire load
range and the full temperature range. Use >1µF capacitor at
the input of LDO Regulators, V
IN
_LDO pins. The input
capacitor lowers the source impedance of the input supply.
Larger capacitor values and lower ESR provides better
PSRR and line transient response. The input capacitor must
be located at a distance of not more then 0.5 inches from the
V
IN
pins of the IC and returned to a clean analog ground.
Any good quality ceramic capacitor can be used as an input
capacitor.
The output capacitor must meet the requirements of
minimum amount of capacitance and ESR for both LDO’s.
The ISL6413 is specifically designed to work with small
ceramic output capacitors. The output capacitor’s ESR
affects stability and output noise. Use an output capacitor
with an ESR of 50m or less to insure stability and optimum
transient response. For stable operation, a ceramic
capacitor, with a minimum value of 3.3µF, is recommended
for V
OUT1
for 300mA output current, and 3.3µF is
recommended for V
OUT2
at 200mA load current. There is no
upper limit to the output capacitor value. Larger capacitor
can reduce noise and improve load transient response,
stability and PSRR. Higher value of output capacitor (10µF)
is recommended for LDO2 when used to power VCO
circuitry in wireless chipsets. The output capacitor should be
located very close to V
OUT
pins to minimize impact of PC
board inductances and the other end of the capacitor should
be returned to a clean analog ground.
PWM Regulator Component Selection
INDUCTOR SELECTION
A 10µH minimum output inductor is used with the ISL6413
PWM section. Values larger then 15µH or less then 10µH
may cause stability problems because of the internal
compensation of the regulator. The important parameters of
the inductor that need to be considered are the current rating
of the inductor and the DC resistance of the inductor. The dc
resistance of the inductor will influence directly the efficiency
of the converter. Therefore, an inductor with lowest dc
resistance should be selected for highest efficiency.
ISL6413
11
In order to avoid saturation of the inductor, the inductor
should be rated at least for the maximum output current plus
the inductor ripple current.
OUTPUT CAPACITOR SELECTION
For best performance, a low ESR output capacitor is
needed. If an output capacitor is selected with an ESR value
120m, its RMS ripple current rating will always meet the
application requirements. The RMS ripple current is
calculated as:
The overall output ripple voltage is the sum of the voltage
spike caused by the output capacitor ESR plus the voltage
ripple caused by charge and discharging the output
capacitor:
Where the highest output voltage ripple occurs at the highest
input voltage VI.
INPUT CAPACITOR SELECTION
Because of the nature of the buck converter having a
pulsating input current, a low ESR input capacitor is required
for best input voltage filtering and minimizing the
interference with other circuits caused by high input voltage
spikes.
The input capacitor should have a minimum value of 10µF
and can be increased without any limit for better input
voltage filtering. The input capacitor should be rated for the
maximum input ripple current calculated as:
The worst case RMS ripple current occurs at D = 0.5.
Ceramic capacitors show good performance because of
their low ESR value, and because they are less sensitive to
voltage transients, compared to tantalum capacitors.
Place the input capacitor as close as possible to the input pin
of the IC for best performance.
Layout Considerations
As for all switching power supplies, the layout is an important
step in the design especially at high peak currents and
switching frequencies. If the layout is not carefully done, the
regulator might show stability problems as well as EMI
problems. Therefore, use wide and short traces for the main
current paths. The input capacitor should be placed as close
as possible to the IC pins as well as the inductor and output
capacitor. Use a common ground node to minimize the
effects of ground noise.
Allocate two board levels as ground planes, with many vias
between them to create a low impedance, high-frequency
plane. Tie all the device ground pins through multiple vias
each to this ground plane, as close to the device as possible.
Also tie the exposed pad on the bottom of the device to this
ground plane.
Refer to application note AN1081.
TABLE 1. RECOMMENDED INDUCTORS
OUTPUT
CURRENT
INDUCTOR
VALUE VENDOR PART # COMMENTS
0mA to
600mA
10µH Coilcraft DO3316P-103
Coilcraft DT3316P-103
Sumida CDR63B-100
Sumida CDRH5D28-100
High
Efficiency
Coilcraft DO1608C-100
Sumida CDRH4D28-100
Smallest
Solution
0mA to
300mA
10µH Coilcraft DS1608C-103 High
Efficiency
Murata LQH4C100K04 Smallest
Solution
TABLE 2. RECOMMENDED CAPACITORS
CAPACITOR
VALUE ESR/m VENDOR PART # COMMENTS
10µF 50 Taiyo Yuden
JMK316BJ106KL
Ceramic
47µF 100 Sanyo 6TPA47M POSCAP
68µF 100 Sprague
594D686X0010C2T
Tantalum
I
RMS C()
O
V
O
1
V
O
V
I
--------
Lf×
-----------------
1
23×
-----------------
××=
V
O
V
O
1
V
O
V
I
--------
Lf×
-----------------






1
8C
O
f××
-------------------------- ESR+


××=
I
RMS
I
Omax()
V
O
V
I
--------
1
V
O
V
I
--------



××=
ISL6413
12
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable.
However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its
use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
ISL6413
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L24.4x4B
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VGGD-2 ISSUE C)
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A2 - - 1.00 9
A3 0.20 REF 9
b 0.18 0.23 0.30 5, 8
D 4.00 BSC -
D1 3.75 BSC 9
D2 2.19 2.34 2.49 7, 8
E 4.00 BSC -
E1 3.75 BSC 9
E2 2.19 2.34 2.49 7, 8
e 0.50 BSC -
k0.25 - - -
L 0.30 0.40 0.50 8
L1 - - 0.15 10
N242
Nd 6 3
Ne 6 3
P- -0.609
θ --129
Rev. 0 10/03
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.

ISL6413IR

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC REG TRPL BUCK/LNR SYNC 24QFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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