9
Synchronization
The typical operating frequency for the converter is 750kHz
if no clock signal is applied to SYNC pin. It is possible to
synchronize the converter to an external clock within a
frequency range from 500kHz to 1000kHz. The device
automatically detects the rising edge of the first clock and
will synchronize immediately to the external clock. If the
clock signal is stopped, the converter automatically switches
back to the internal clock and continues operation without
interruption. The switch over will be initiated if no rising edge
on the SYNC pin is detected for a duration of two internal
1.3µs clock cycles.
Soft Start
As the EN_PWM (Enable) pin goes high, the soft-start
function will generate an internal voltage ramp. This causes
the start-up current to slowly rise preventing output voltage
overshoot and high inrush currents. The soft-start duration is
typically 5.5ms with 750kHz switching frequency. When the
soft-start is completed, the error amplifier will be connected
directly to the internal voltage reference. The SYNC input is
ignored during soft start.
Enable PWM
Logic low on EN_PWM pin forces the PWM section into
shutdown. In shutdown all the major blocks of the PWM
including power switches, drivers, voltage reference, and
oscillator are turned off.
Power Good (PG_PWM)
When chip is enabled, this output is HIGH, when V
OUT
is
within 8% of 1.8V and active low outside this range. When
the PWM is disabled, the output is active low. PG_PWM
is
the complement of PG_PWM.
Leave the PG_PWM pin unconnected when not used.
PWM Overvoltage and Overcurrent Protection
The PWM output current is sampled at the end of each PWM
cycle. Should it exceed the overcurrent limit, a 4 bit up/down
counter counts up two LSB. Should it not be in overcurrent
the counter counts down one LSB (but counter will not
"rollover" or count below 0000). If >33% of the PWM cycles
go into overcurrent, the counter rapidly reaches count 1111
and the PWM output is shut down and the softstart counter is
reset. After 16 clocks the PWM output is enabled and the SS
cycle is started.
If V
OUT
exceeds the overvoltage limit for 32 consecutive
clock cycles the PWM output is shut off and the SS counters
reset. The softstart cycle will not be started until EN or V
IN
are toggled.
PG_LDO
PG_LDO is an open drain pulldown NMOS output that will
sink 1mA at 0.4V max. It goes to the active low state if either
LDO output is out of regulation by more than 15%. When the
LDO is disabled, the output is active low.
LDO Regulators
Each LDO consists of a 1.184V reference, error amplifier,
MOSFET driver, P-Channel pass transistor, dual-mode
comparator and internal feedback voltage divider.
The 1.2V band gap reference is connected to the error
amplifier’s inverting input. The error amplifier compares this
reference to the selected feedback voltage and amplifies the
difference. The MOSFET driver reads the error signal and
applies the appropriate drive to the P-Channel pass
transistor. If the feedback voltage is lower then the reference
voltage, the pass transistor gate is pulled lower, allowing
more current to pass and increasing the output voltage. If the
feedback voltage is higher then the reference voltage, the
pass transistor gate is driven higher, allowing less current to
pass to the output. The output voltage is fed back through an
internal resistor divider connected to V
OUT1
/V
OUT2
pins.
Internal P-Channel Pass Transistors
The ISL6413 LDO Regulators features a typical 0.5Ω
R
ds(ON)
P-channel MOSFET pass transistors. This provides
several advantages over similar designs using PNP bipolar
pass transistors. The P-Channel MOSFET requires no base
drive, which reduces quiescent current considerably. PNP
based regulators waste considerable current in dropout
when the pass transistor saturates. They also use high base
drive currents under large loads. The ISL6413 does not
suffer from these problems.
Integrated RESET for MAC/ Baseband Processors
The ISL6413 includes a microprocessor supervisory block.
This block eliminates the extra RESET IC and external
components needed in wireless chipset applications. This
block performs a single function; it asserts a RESET signal
whenever the V
IN
supply voltage decreases below a preset
threshold, keeping it asserted for a programmable time (set
by external capacitor CT) after the V
IN
pin voltage has risen
above the RESET threshold.
The push pull output stage of the reset circuit provides both
an active-Low and an active-HIGH output. The RESET
threshold for ISL6413 is 2.630V typical.
UVLO Reset threshold is always lower then RESET. This
insures that as V
IN
falls, reset goes low before LDOs and
PWM are shuts off.
Output Voltages
The ISL6413 provides fixed output voltages for use in
Wireless Chipset applications. Internal trimmed resistor
networks set the typical output voltages as shown here:
V
OUT_PWM
= 1.8V; V
OUT1
= 2.84V; V
OUT2
= 2.84V.
Integrator Circuitry
The ISL6413 LDO Regulators uses an external 33nF
compensation capacitor for minimizing load and line
regulation errors and for lowering output noise. When the
output voltage shifts due to varying load current or input
ISL6413
