13
FN8216.3
February 20, 2008
Voltage Reference
The voltage reference to the A/D and D/A converters on the
X96012, may be driven from the on-chip voltage reference,
or from an external source via the VREF pin. Bit VRM in
Control Register 0 selects between the two options. See
Figure 5.
The default value of VRM is “0”, which selects the internal
reference. When the internal reference is selected, it’s
output voltage is also an output at pin VREF with a nominal
value of 1.21 V. If an external voltage reference is preferred,
the VRM bit of the Control Register 0 must be set to “1”.
A/D Converter
The X96012 contains a general purpose, on-chip, 8-bit
Analog to Digital (A/D) converter whose output is available at
the Status Register as bits AD[7:0]. By default these output
bits are used to select a row in the look-up tables associated
with the X96012’s Current Generators. When bit ADCfiltOff
is “0” (default), bits AD[7:0] are updated each time the ADC
performs four consecutive conversions with the same exact
result at the 6 MSBs. When bit ADCfiltOff is “1”, these bits
are updated after every ADC conversion.
A block diagram of the A/D converter is shown in Figure 6.
The voltage reference input (see “Voltage Reference” on
page 13), sets the maximum amplitude of the ramp
generator output. The A/D converter input signal (see “A/D
Converter Input Select” on page 13 for details) is compared
to the ramp generator output. The control and encode logic
produces a binary encoded output, with a minimum value of
00h (0
10
), and a full scale output value of FFh (255
10
).
The A/D converter input voltage range (VIN
ADC
) is from 0V
to V(VREF).
A/D Converter Input Select
The input signal to the A/D converter on the X96012, may be
the output of the on-chip temperature sensor, or an external
source via the VSENSE pin. Bit ADCIN in Control register 0
selects between the two options. See Figure 7. It’s default
value is “0”, which selects the internal temperature sensor.
If an external source is intended as the input to the A/D
converter, the ADCIN bit of the Control register 0 must be set
to “1”.
A/D Converter Range
From Figure 6 we can see that the operating range of the
A/D converter input depends on the voltage reference. And
from Figure 7 we see that the internal temperature Sensor
output also varies with the voltage reference (VREF).
Table 4 summarizes the voltage range restrictions on the
VSENSE and VREF pins in different configurations.
VRM: BIT 2 IN CONTROL REGISTER 0
VREF PIN
ON-CHIP
A/D CONVERTER AND
VOLTAGE
REFERENCE
D/A CONVERTERS REFERENCE
FIGURE 5. VOLTAGE REFERENCE STRUCTURE
TABLE 4. VSENSE AND VREF RANGES
VREF A/D CONVERTER INPUT RANGES
Internal Internal Temp Sensor Not Applicable
Internal VSense Pin 0 V(VSense)
V(VREF)
External VSense Pin 0 V(VREF) 1.3 V
0 V(VSense) V(VREF)
External Internal Temp. Sensor Not a Valid Case
All voltages referred to V
SS
RAMP
GENERATOR
A/D CONVERTER INPUT
FROM VREF
CLOCK
CONTROL AND
ENCODE LOGIC
CONVERSION RESET
A/D CONVERTER
OUTPUT
(TO LUTS
AND STATUS
REGISTER)
8
COMPARATOR
VSENSE
ON-CHIP
TO A/D
ADCIN: BIT 3 IN CONTROL REGISTER 0.
TEMPERATURE
SENSOR
PIN
VREF
CONVERTER
INPUT
FIGURE 7. A/D CONVERTER INPUT SELECT STRUCTURE
X96012
14
FN8216.3
February 20, 2008
Look-Up Tables
The X96012 memory array contains two 64-byte look-up
tables. One is associated to pin I1’s output current generator
and the other to pin I2’s output current generator, through
their corresponding D/A converters. The output of each
look-up table is the byte contained in the selected row. By
default these bytes are the inputs to the D/A converters
driving pins I1 and I2.
The byte address of the selected row is obtained by adding
the look-up table base address (90h for LUT1, and D0h for
LUT2) and the appropriate row selection bits. See Figure 9.
By default, the look-up table selection bits are the 6
MSBs of the A/D converter output. Alternatively, the A/D
converter can be bypassed and the six row selection bits
are the six LSBs of Control Registers 1 and 2, for the
LUT1 and LUT2 respectively. The selection between
these options is illustrated in Figure 10, and described in
I2DS: Current Generator 2 Direction Select Bit (Non-volatile)”
on page 9, and “Control Register 2” on page 10.
Current Generator Block
The Current Generator pins I1 and I2 are outputs of two
independent current mode D/A converters.
D/A Converter Operation
The Block Diagram for each of the D/A converters is shown
in Figure 8.
The input byte of the D/A converter selects a voltage on the
non-inverting input of an operational amplifier. The output of
the amplifier drives the gate of a FET, whose source is
connected to ground via resistor R
1
or R
2
. This node is also
fed back to the inverting input of the amplifier. The drain of
the FET is connected to the output current pin (I1 or I2) via a
“polarity select” circuit block.
+
-
I1 OR I2 PIN
R1 OR R2 PIN
R1_EXTERNAL OR R2_EXTERNAL
I1DS OR I2DS: BITS
VSS VSS
I1FSO[1:0]
R1_LOW_CURRENT OR
R1_MIDDLE_CURRENT OR
R1_HIGH_CURRENT OR
VREF
OPTIONAL EXTERNAL RESISTOR
SELECT
CIRCUIT
POLARITY
VCC
VOLTAGE
6 OR 7 IN CONTROL
REGISTER 0.
DIVIDER
DAC1 OR
DAC2
INPUT BYTE
VSS
VSS
OR I2FSO[1:0]
BITS 1 AND 0, OR
3 AND 2 IN CONTROL
REGISTER 5
11
10 01
00
R2_HIGH_CURRENT
R2_MIDDLE_CURRENT
R2_LOW_CURRENT
FIGURE 8. D/A CONVERTER BLOCK DIAGRAM
X96012
15
FN8216.3
February 20, 2008
By examining the block diagram in Figure 8, we see that the
maximum current through pin I1 is set by fixing values for
V(VREF) and R
1
. The output current can then be varied by
changing the data byte at the D/A converter input.
In general, the magnitude of the current at the D/A converter
output pins (I1, I2) may be calculated using Equation 1:
where x = 1, 2 and N is the decimal representation of the
input byte to the corresponding D/A converter.
The value for the resistor Rx (x = 1, 2) determines the full
scale output current that the D/A converter may sink or
source. The full scale output current has a maximum value of
±3.2mA, which is obtained using a resistance of 255 for Rx.
This resistance may be connected externally to pin Rx of the
X96012, or may be selected from one of three internal values.
Bits I1FSO1 and I1FSO0 select the full scale output current
setting for I1 as described in “I1FSO1 - I1FSO0: Current
Generator 1 Full Scale Output Set Bits (Non-volatile)” on
page 12. Bits I2FSO1 and I2FSO0 select the maximum
current setting for I2. When an internal resistor is selected for
R
1
or R
2
, then no resistor should be connected externally at
the corresponding pin.
Bits I1DS and I2DS in Control Register 0 select the direction
of the currents through pins I1 and I2 independently (see
“I1DS: Current Generator 1 Direction Select Bit (Non-volatile)”
on page 9 and “Control and Status Registers” on page 9).
D/A Converter Output Current Response
When the D/A converter input data byte changes by an
arbitrary number of bits, the output current changes from an
initial current level (I
x
) to some final level (I
x
+ I
x
). The
transition is monotonic and glitchless.
D/A Converter Control
The data byte inputs of the D/A converters can be controlled
in three ways:
1) With the A/D converter and through the look-up tables
(default),
2) Bypassing the A/D converter and directly accessing the
look-up tables,
3) Bypassing both the A/D converter and look-up tables, and
directly setting the D/A converter input byte.
The options are summarized in Tables 5 and 6.
DAC 2
8
D0H
D0H
10FH
8
LUT2
6
LUT2 ROW
OUT
D1
D0
SELECT
D2DAS: BIT 7 OF
D2DA[7:0] : CONTROL REGISTER 4
SELECTION BITS
A
D
D
E
R
8
8
INPUT BYTE
CONTROL REGISTER 5
DAC 1
8
90H
90H
CFH
8
LUT1
6
LUT1 ROW
OUT
D1
D0
SELECT
D1DAS: BIT 5 OF
D1DA[7:0] : CONTROL REGISTER 3
SELECTION BITS
A
D
D
E
R
8
8
INPUT BYTE
CONTROL REGISTER 5
FIGURE 9. LOOK-UP TABLE (LUT) OPERATION
Ix V Vref 384 Rx N=
(EQ. 1)
TABLE 5. D/A CONVERTER 1 ACCESS SUMMARY
L1DAS D1DAS CONTROL SOURCE
0 0 A/D converter through LUT1 (Default)
1 0 Bits L1DA5 - L1DA0 through LUT1
X 1 Bits D1DA7 - D1DA0
NOTE: “X” = Don’t Care Condition (May be either “1” or “0”)
TABLE 6. D/A CONVERTER 2 ACCESS SUMMARY
L2DAS D2DAS CONTROL SOURCE
0 0 A/D converter through LUT2 (Default)
1 0 Bits L2DA5 - L2DA0 through LUT2
X 1 Bits D2DA7 - D2DA0
NOTE: “X” = Don’t Care Condition (May be either “1” or “0”)
X96012

X96012V14I

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC CNTRLR UNIV MEM/DAC 14-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
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