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X96012V14I

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
19
FN8216.3
February 20, 2008
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte. Refer to Figure 16. This byte includes
three parts:
• The four MSBs (SA7 - SA4) are the Device Type
Identifier, which must always be set to 1010 in order to
select the X96012.
• The next three bits (SA3 - SA1) are the Device Address bits
(AS2 - AS0). To access any part of the X96012’s memory,
the value of bits AS2, AS1, and AS0 must correspond to the
logic levels at pins A2, A1, and A0 respectively.
• The LSB (SA0) is the R/W
bit. This bit defines the operation
to be performed on the device being addressed. When the
R/W
bit is “1”, then a Read operation is selected. A “0”
selects a Write operation (refer to Figure 16).
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence is correctly
issued (including the final STOP condition), the X96012
initiates an internal high voltage write cycle. This cycle
typically requires 5ms. During this time, any Read or Write
command is ignored by the X96012. Write Acknowledge
Polling is used to determine whether a high voltage write
cycle is completed.
During acknowledge polling, the master first issues a START
condition followed by a Slave Address Byte. The Slave
Address Byte contains the X96012’s Device Type Identifier
and Device Address. The LSB of the Slave Address (R/W
)
can be set to either 1 or 0 in this case. If the device is busy
within the high voltage cycle, then no ACK is returned. If the
high voltage cycle is completed, an ACK is returned and the
master can then proceed with a new Read or Write
operation. Refer to Figure 17.
Byte Write Operation
In order to perform a Byte Write operation to the memory
array, the Write Enable Latch (WEL) bit of the Control 6
Register must first be set to “1”. See “WEL: Write Enable
Latch (Volatile)” on page 12.
For any Byte Write operation, the X96012 requires the Slave
Address Byte, an Address Byte, and a Data Byte. See
Figure 18. After each of them, the X96012 responds with an
ACK. The master then terminates the transfer by generating a
STOP condition. At this time, if all data bits are volatile, the
X96012 is ready for the next read or write operation. If some
bits are nonvolatile, the X96012 begins the internal write cycle
to the nonvolatile memory. During the internal nonvolatile write
cycle, the X96012 does not respond to any requests from the
master. The SDA output is at high impedance.
A Byte Write operation can access bytes at locations 00h
through FEh directly, when setting the Address Byte to 00h
through FEh respectively. Setting the Address Byte to FFh
accesses the byte at location 100h. The other sixteen bytes,
at locations FFh and 101h through 10Fh can only be
accessed using Page Write operations. The byte at location
FFh can only be written using a “Page Write” operation.
Writing to Control bytes which are located at byte addresses
80h through 8Fh is a special case described in “Writing to
Control Registers” on page 20.
Page Write Operation
The 2176-bit memory array is physically realized as one
contiguous array, organized as 17 pages of 16 bytes each. A
“Page Write” operation can be performed to any of the GPM
or LUT pages. In order to perform a Page Write operation to
the memory array, the Write Enable Latch (WEL) bit in
Control register 6 must first be set See “WEL: Write Enable
Latch (Volatile)” on page 12.
A Page Write operation is initiated in the same manner as
the byte write operation; but instead of terminating the write
cycle after the first data byte is transferred, the master can
transmit up to 16 bytes (see Figure 19). After the receipt of
each byte, the X96012 responds with an ACK, and the
internal byte address counter is incremented by one. The
page address remains constant. When the counter reaches
the end of the page, it “rolls over” and goes back to the first
byte of the same page.
ACK RETURNED?
ISSUE SLAVE
ADDRESS BYTE
(READ OR WRITE)
BYTE LOAD COMPLETED BY ISSUING
STOP. ENTER ACK POLLING
ISSUE STOP
ISSUE START
NO
YES
NO
CONTINUE NORMAL READ OR
WRITE COMMAND SEQUENCE
PROCEED
YES
COMPLETE. CONTINUE COMMAND
SEQUENCE.
HIGH VOLTAGE
ISSUE STOP
FIGURE 17. ACKNOWLEDGE POLLING SEQUENCE
X96012
20
FN8216.3
February 20, 2008
For example, if the master writes 12 bytes to a 16-byte page
starting at location 11 (decimal), the first 5 bytes are written
to locations 11 through 15, while the last 7 bytes are written
to locations 0 through 6 within that page. Afterwards, the
address counter would point to location 7. If the master
supplies more than 16 bytes of data, then new data
overwrites the previous data, one byte at a time. See
Figure 20.
The master terminates the loading of Data Bytes by issuing
a STOP condition, which initiates the nonvolatile write cycle.
As with the Byte Write operation, all inputs are disabled until
completion of the internal write cycle.
A Page Write operation cannot be performed on the page at
locations 80h through 8Fh. The next section describes the
special cases within that page.
A Page Write operation starting with byte address FFh,
accesses the page between locations 100h and 10Fh. The
first data byte of such operation is written to location 100h.
Writing to Control Registers
The byte at location 80h, 85h, and 86h are written using Byte
Write operations. They cannot be written using a Page Write
operation.
Control bytes 1 through 4, at locations 81h through 84h
respectively, are written during a single operation (see
Figure 21). The sequence must be: a START, followed by a
Slave Address byte, with the R/W
bit equal to “0”, followed by
81h as the Address Byte, and then followed by exactly four
Data Bytes, and a STOP condition. The first data byte is
written to location 81h, the second to 82h, the third to 83h,
and the last one to 84h.
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
ADDRESS
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE SLAVE
A
C
K
1
0
100
A
C
K
WRITE
SIGNAL AT SDA
FIGURE 18. BYTE WRITE SEQUENCE
2 < n < 16
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT SDA
S
T
A
R
T
SLAVE
ADDRESS
ADDRESS
BYTE
A
C
K
A
C
K
1
0
100
DATA BYTE (1)
S
T
O
P
A
C
K
A
C
K
DATA BYTE (N)
WRITE
FIGURE 19. PAGE WRITE OPERATION
5 BYTES
7 BYTES
ADDRESS = 6
5 BYTES
ADDRESS POINTER
ADDRESS = 15
ADDRESS = 11
ENDS UP HERE
ADDRESS = 7
ADDRESS = 0
FIGURE 20. EXAMPLE: WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 11
X96012
21
FN8216.3
February 20, 2008
The four registers Control 1 through 4, have a nonvolatile
and a volatile cell for each bit. At power-up, the content of
the nonvolatile cells is automatically recalled and written to
the volatile cells. The content of the volatile cells controls the
X96012’s functionality. If bit NV1234 in the Control 0 register
is set to “1”, a Write operation to these registers writes to
both the volatile and nonvolatile cells. If bit NV1234 in the
Control 0 register is set to “0”, a Write operation to these
registers only writes to the volatile cells. In both cases the
newly written values effectively control the X96012, but in
the second case, those values are lost when the part is
powered down.
If bit NV1234 is set to “0”, a Byte Write operation to Control
registers 0 or 5 causes the value in the nonvolatile cells of
Control registers 1 through 4 to be recalled into their
corresponding volatile cells, as during power-up. This
doesn’t happen when the WP
pin is LOW, because Write
Protection is enabled. It is generally recommended to
configure Control registers 0 and 5 before writing to Control
registers 1 through 4.
When reading any of the control registers 1, 2, 3, or 4, the
Data Bytes are always the content of the corresponding
nonvolatile cells, even if bit NV1234 is "0". See “Control and
Status Registers” on page 9.
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (see Figure 22). The master
initiates the operation issuing the following sequence: a
START, the Slave Address byte with the R/W
bit set to “0”,
an Address Byte, a second START, and a second Slave
Address byte with the R/W
bit set to “1”. After each of the
three bytes, the X96012 responds with an ACK. Then the
X96012 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of
the last Data Byte. See Figure 22.
The Data Bytes are from the memory location indicated by
an internal pointer. This pointer initial value is determined by
the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 10Fh the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
A Read operation internal pointer can start at any memory
location from 00h through FEh, when the Address Byte is
00h through FEh respectively. But it starts at location 100h if
the Address Byte is FFh.
When reading any of the control registers 1, 2, 3, or 4, the
Data Bytes are always the content of the corresponding
nonvolatile cells, even if bit NV1234 is "0". See “Control and
Status Registers” on page 9.
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT SDA
S
T
A
R
T
SLAVE
ADDRESS
ADDRESS
BYTE = 81h
A
C
K
A
C
K
10100
DATA BYTE FOR
CONTROL 1
S
T
O
P
A
C
K
A
C
K
DATA BYTE FOR
CONTROL 4
WRITE
11000 000
FOUR DATA BYTES
FIGURE 21. WRITING TO CONTROL REGISTERS 1, 2, 3 AND 4
SIGNALS
FROM THE
MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT
SDA
S
T
A
R
T
SLAVE
ADDRESS
WITH
R/W
= 0
ADDRESS
BYTE
A
C
K
A
C
K
1
0
100
S
T
O
P
A
C
K
1
1
100
SLAVE
ADDRESS
WITH
R/W
= 1
A
C
K
S
T
A
R
T
LAST READ
DATA BYTE
FIRST READ
DATA BYTE
A
C
K
FIGURE 22. READ SEQUENCE
X96012
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

X96012V14I

Mfr. #:
Buy X96012V14I
Manufacturer:
Renesas / Intersil
Description:
IC CNTRLR UNIV MEM/DAC 14-TSSOP
Lifecycle:
New from this manufacturer.
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