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X96012V14I

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
4
FN8216.3
February 20, 2008
I
R
Current from pin R1 or R2 to VSS 0 3200 µA
V
POR
Power-on Reset Threshold
Voltage
1.5 2.8 V
V
CC
Ramp V
CC
Ramp Rate 0.2 50 mV/µs
V
ADCOK
ADC Enable Minimum Voltage Figure 11 2.6 2.8 V
NOTES:
2. These parameters are periodically sampled and not 100% tested.
3. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
4. The device goes into Standby: 200ns after any STOP, except those that initiate a nonvolatile write cycle. It goes into Standby t
WC
after a STOP
that initiates a nonvolatile write cycle. It also goes into Standby 9 clock cycles after any START that is not followed by the correct Slave Address
Byte.
5. t
WC
is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
6. For this range of V(V
REF
) the full scale sink mode current at I1 and I2 follows V(V
REF
) with a linearity error smaller than 1%.
7. These parameters are periodically sampled and not 100% tested.
8. TCO
ref
= [Max V(V
REF
) - Min V(V
REF
)] x 10
6
/(1.21V x +140°C).
Electrical Specifications Conditions are as follows, unless otherwise specified. All typical values are for T
A
= +25°C and 5V at pin V
CC
.
Maximum and minimum specifications are over the recommended operating conditions. All voltages are
referred to the voltage at pin V
SS
. All bits in control registers are “0”. 255, 0.1%, resistor connected between
R
1
and V
SS
, and another between R
2
and V
SS
. 400kHz TTL input at SCL. SDA pulled to V
CC
through an
external 2k resistor. 2-wire interface in “standby” (see Notes 9 and 10 on page 5). WP
, A0, A1, and A2 floating.
V
REF
pin unloaded. (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 3) TYP
MAX
(Note 3) UNIT
D/A Converter Characteristics (See “Electrical Specifications” table starting on page 3 for standard conditions).
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 3) TYP
MAX
(Note 3) UNIT
IFS
00
I1 or I2 Full Scale Current, with External Resistor
Setting
(Notes 9, 12) 1.56 1.58 1.6 mA
(Notes 2, 9, 13) 3.2 mA
IFS
01
I1 or I2 Full Scale Current, with Internal Low
Current Setting Option
DAC input Byte = FFh,
Source or sink mode, V(I1) and V(I2)
are V
CC
- 1.2V in source mode and
1.2V in sink mode.
(Notes 10, 11)
0.3 0.4 0.5 mA
IFS
10
I1 or I2 Full Scale Current, with Internal Middle
Current Setting Option
0.64 0.85 1.06 mA
IFS
11
I1 or I2 Full Scale Current, with Internal High
Current Setting Option
11.31.6mA
Offset
DAC
I1 or I2 D/A Converter Offset Error 1 1 LSB
FSError
DAC
I1 or I2 D/A Converter Full Scale Error -2 2 LSB
DNL
DAC
I1 or I2 D/A Converter Differential Nonlinearity -0.5 0.5 LSB
INL
DAC
I1 or I2 D/A Converter Integral Nonlinearity with
Respect to a Straight Line Through 0 and the Full
Scale Value
-1 1 LSB
V
ISink
I1 or I2 Sink Voltage Compliance (Note 12) 1.2 V
CC
V
(Notes 2, 13) 2.5 V
CC
V
V
ISource
I1 or I2 Source Voltage Compliance (Note 12) 0 V
CC
- 1.2 V
(Notes 2, 13) 0 V
CC
- 2.5 V
X96012
5
FN8216.3
February 20, 2008
.
I
OVER
I1 or I2 Overshoot on D/A Converter Data Byte
Transition
DAC input byte changing from 00h to
FFh and vice versa, V(I1) and V(I2)
are V
CC
- 1.2V in source mode and
1.2V in sink mode. (Note 2)
0µA
I
UNDER
I1 or I2 Undershoot on D/A Converter Data Byte
Transition
0µA
t
rDAC
I1 or I2 Rise Time on D/A Converter Data Byte
Transition; 10% to 90%
530µs
TCO
I1I2
Temperature Coefficient of Output Current I1 or
I2 when Using Internal Resistor Setting
Bits I1FSO[1:0] ¦ 00
2
or
Bits I2FSO[1:0] ¦ 002,
VRMbit = “1”
See Figure 8
±200 ppm/°C
NOTES:
9. DAC input Byte = FFh, Source or sink mode.
10. LSB is defined as divided by the resistance between R
1
or R
2
to V
SS
.
11. Offset
DAC
: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is expressed in
LSB. FSError
DAC
: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It is
expressed in LSB. The Offset
DAC
is subtracted from the measured value before calculating FSError
DAC
.DNL
DAC
: The Differential Non-Linearity of
a DAC is defined as the deviation between the measured and ideal incremental change in the output of the DAC, when the input changes by one
code step. It is expressed in LSB. The measured values are adjusted for Offset and Full Scale Error before calculating DNL
DAC
. INL
DAC
: The
Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjusting the measured transfer
curve for Offset and Full Scale Error. It is expressed in LSB.
12. V(I1) and V(I2) are V
CC
- 1.2V in source mode and 1.2V in sink mode. In this range the current at I1 or I2 varies < 1%.
13. The maximum current, sink or source, can be set with an external resistor to 3.2 mA with a minimum V
CC
= 4.5V. The compliance
voltage changes to 2.5V from the sourcing rail, and the current variation is < 1%.
D/A Converter Characteristics (See “Electrical Specifications” table starting on page 3 for standard conditions). (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 3) TYP
MAX
(Note 3) UNIT
2
3
V(VRef)
255
x
[]
A/D Converter Characteristics (See “Electrical Specifications” table starting on page 3 for standard conditions).
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 3) TYP
MAX
(Note 3) UNIT
ADCTIME A/D Converter Conversion Time Proportional to A/D converter input voltage.
This value is maximum at full scale input of
A/D converter. ADCfiltOff = “1”
9ms
RIN
ADC
VSense Pin Input Resistance VSense as an input, ADCIN bit = “1” 100 k
CIN
ADC
VSense Pin Input Capacitance VSense as an input, ADCIN bit = “1”,
Frequency = 1 MHz. (Note 2)
17pF
VIN
ADC
VSense Input Signal Range This is the A/D Converter Dynamic
Range. ADCIN bit = “1”
0V(VRef)V
THE ADC IS MONOTONIC
Offset
ADC
A/D Converter Offset Error (Notes 2, 14) ±1 LSB
FSError
ADC
A/D Converter Full Scale Error ±1 LSB
DNL
ADC
A/D Converter Differential
Nonlinearity
±0.5 LSB
INL
ADC
A/D Converter Integral Nonlinearity ±1 LSB
TempStep
ADC
Temperature Step Causing One
Step Increment of ADC Output
(Note 2) 0.52 0.55 0.58 °C
Out25
ADC
ADC Output at +25°C 01110101
2
X96012
6
FN8216.3
February 20, 2008
NOTES:
14. LSB” is defined as V(VRef)/255, “Full-Scale” is defined as V(VRef).
15. Offset
ADC
: For an ideal converter, the first transition of its transfer curve occurs at above zero. Offset error is the amount of
deviation between the measured first transition point and the ideal point. FSError
ADC
: For an ideal converter, the last transition of its transfer
curve occurs at . Full-Scale Error is the amount of deviation between the measured last transition point and the ideal point,
after subtracting the Offset from the measured curve. DNL
ADC
: DNL is defined as the difference between the ideal and the measured code
transitions for successive A/D code outputs expressed in LSBs. The measured transfer curve is adjusted for Offset and Full-scale errors before
calculating DNL. INL
ADC
: The deviation of the measured transfer function of an A/D converter from the ideal transfer function. The INL error is
also defined as the sum of the DNL errors starting from code 00h to the code where the INL measurement is desired. The measured transfer
curve is adjusted for Offset and Full scale errors before calculating INL.
A/D Converter Characteristics (See “Electrical Specifications” table starting on page 3 for standard conditions).
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 3) TYP
MAX
(Note 3) UNIT
0.5 x V(VRef)
255
[]
254.5
x V(VRef)
255
[]
2-Wire Interface AC Characteristics
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 3) TYP
MAX
(Note 3) UNITS
f
SCL
SCL Clock Frequency See “2-Wire Interface Test
Conditions” on page 6
See Figures 1, 2, 3.
1
(Note 18)
400 kHz
t
IN
(Note 2) Pulse width Suppression Time at Inputs 50 ns
t
AA
(Note 2) SCL Low to SDA Data Out Valid 900 ns
t
BUF
(Note 2) Time the Bus Free Before Start of New
Transmission
1300 ns
t
LOW
Clock Low Time 1.3 1200
(Note 18)
µs
t
HIGH
Clock High Time 0.6 1200
(Note 18)
µs
t
SU:STA
Start Condition Set-up Time 600 ns
t
HD:STA
Start Condition Hold Time 600 ns
t
SU:DAT
Data In Set-up Time 100 ns
t
HD:DAT
Data In Hold Time 0 µs
t
SU:STO
Stop Condition Set-up Time 600 ns
t
DH
Data Output Hold Time 50 ns
t
R
(Note 2) SDA and SCL Rise Time 20 +0.1Cb
(Note 16)
300 ns
t
F
(Note 2) SDA and SCL Fall Time 20 +0.1Cb
(Note 16)
300 ns
t
SU:WP
(Note 2) WP Set-up Time 600 ns
t
HD:WP
(Note 2) WP Hold Time 600 ns
Cb (Note 2) Capacitive Load for Each Bus Line 400 pF
2-Wire Interface Test Conditions
Input Pulse Levels 10% to 90% of V
CC
Input Rise and Fall Times, between 10% and 90% 10ns
Input and Output Timing Threshold Level 1.4V
External Load at Pin SDA 2.3k to V
CC
and 100pF to V
SS
X96012
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

X96012V14I

Mfr. #:
Buy X96012V14I
Manufacturer:
Renesas / Intersil
Description:
IC CNTRLR UNIV MEM/DAC 14-TSSOP
Lifecycle:
New from this manufacturer.
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