LE2432RDXA
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13
7)-3. Sequential Read
The sequential read operation is initiated by either a current address read or random read. If the
EEPROM receives acknowledgement 0 after 8-bit read data, the read address is incremented and the
next 8-bit read data outputs. The current address will roll over and returns address zero if it reaches the
last address of the last page. The sequential read can be continued after roll over. The sequential read is
terminated if the EEPROM receives no acknowledgement and a following stop condition.
D7 D6 ~ D1 D0
Data(n)
S
D
A
Device Address
0 1 0 1
R
Start
A
C
K
Data(n+1) Data(n+2)
R/W
D7 D6 ~ D1 D0
A
C
K
D7 D6 ~ D1 D0
A
C
K
A
C
K
Access from master device
NO ACK
Sto
p
Data(n+x)
D7 D6 ~ D1 D0
ACK
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Application Notes
1) Software reset function
Software reset (start condition + 9 dummy clock cycles + start condition), shown in the figure below, is
executed in order to avoid erroneous operation after power-on and to reset while the command input
sequence. During the dummy clock input period, the SDA bus must be opened (set to high by a pull-up
resistor). Since it is possible for the ACK output and read data to be output from the EEPROM during
the dummy clock period, forcibly entering H will result in an overcurrent flow.
Note that this software reset function does not work during the internal write cycle.
2) Pull-up resistor of SDA pin
Due to the demands of the I
2
C bus protocol function, the SDA pin must be connected to a pull-up resistor
(with a resistance from several k to several tens of k) without fail. The appropriate value must be
selected for this resistance (R
PU
) on the basis of the V
IL
and I
IL
of the microcontroller and other devices
controlling this product as well as the V
OL
– I
OL
characteristics of the product. Generally, when the
resistance is too high, the operating frequency will be restricted; conversely, when it is too low, the
operating current consumption will increase.
R
PU
maximum value
The maximum resistance must be set in such a
way that the bus potential, which is determined
by the sum total (I
L
) of the input leaks of the
devices connected to the SDA bus and by R
PU
,
can completely satisfy the input high level (V
IH
min) of the microcontroller and EEPROM.
However, a resistance value that satisfies SDA
rise time tR and fall time tF must be set.
R
PU
maximum value = (V
DD
V
IH
) / I
L
Example: When V
DD
= 3.0 V and I
L
= 2 A
R
PU
maximum value = (3.0 V 3.0 V 0.8) / 2 A = 300 k
R
PU
minimum value
A resistance corresponding to the low-level output voltage (V
OL
max) of EEPROM must be set.
R
PU
minimum value = (V
DD
V
OL
) / I
OL
Example: When V
DD
= 3.0 V, V
OL
= 0.4 V and I
OL
= 1 mA
R
PU
minimum value = (3.0 V 0.4) / 1 mA = 2.6 k
Recommended R
PU
setting
R
PU
is set to strike a good balance between the operating frequency requirements and power
consumption. If it is assumed that the SDA load capacitance is 50 pF and the SDA output data strobe
time is 500 ns, R
PU
will be about R
PU
= 500 ns/50 pF = 10 k.
Start
Condition
Start
Condition
SCL
SDA
1
2
8
9
Dummy clock x 9
Master
Device
EEPROM
SDA
C
BUS
R
PU
I
L
I
L
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15
3) Precautions when turning on the power
This product contains a power-on reset circuit for preventing the inadvertent writing of data when the
power is turned on. The following conditions must be met in order to ensure stable operation of this
circuit. No data guarantees are given in the event of an instantaneous power failure during the internal
write operation.
symbol Parameter
Spec.
Unit
Min. Typ. Max.
t
RISE
Power rise time 100 ms
t
OFF
Power off time 10 ms
V
bot
Power bottom voltage 0.2 V
Notes:
1) The SDA pin must be set to high and the SCL pin to low or high.
2) Steps must be taken to ensure that the SDA and SCL pins are not placed in a high-impedance state.
A. If it is not possible to satisfy the instruction 1 in Note above, and SDA is set to low during
power rise
After the power has stabilized, the SCL and SDA pins must be controlled as shown below, with both pins
set to high.
B. If it is not possible to satisfy the instruction 2 in Note above
After the power has stabilized, software reset must be executed.
C. If it is not possible to satisfy the instructions both 1 and 2 in Note above
After the power has stabilized, the steps in A must be executed, then software reset must be executed.
4) Noise filter for the SCL and SDA pins
This product contains a filter circuit for eliminating noise at the SCL and SDA pins. Pulses of 100 ns or
less are not recognized because of this function.
5) Function to inhibit writing when supply voltage is low
This product contains a supply voltage monitoring circuit that inhibits inadvertent writing below the
guaranteed operating supply voltage range. The data is protected by ensuring that write operations are
not started at voltages (typ.) of 1.3 V and below.
V
DD
0V
tOFF
tRISE
Vbot
V
DD
SCL
SDA
tLOW
tDH
tSU.DAT
V
DD
SCL
SDA
tSU.DAT

LE2432RDXATDG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
EEPROM 32K BIT I2C FASTPLUS EEP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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