LE2432RDXA
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7
Bus timing
Write timing
Pin Function
SCL (Serial clock)
The SCL signal is used to control serial input data timing. The SCL is used to latch input data synchronously
at the rising edge and read output data synchronously at the falling edge.
SDA (Serial input / output data)
The SDA pin is bidirectional for serial data transfer. It is an open-drain structure that needs to be pulled up by
resistor.
WP (Write protect)
When the WP input is high, write protection is enabled. When WP input is either low or floating, write
protection is disabled. The read operation is always activated irrespective of the WP pin status.
V
DD
2 (Power supply for WP pin pull-up)
V
DD
2 pin is for the pull-up power supply to WP pin. Voltage impression of 0.5 V to V
DD
+0.5 V is permitted
like other pins about the pin voltage.
Write Data
Acknowledge
Stop
condition
Start
condition
t
WC
SCL
SDA
D0
t
SU.DAT
t
BUF
t
SU.STO
t
R
SCL
SDA/IN
SDA/OUT
t
SU.STA
t
HD.DAT
t
HIGH
t
LOW
t
DH
t
AA
t
F
t
HD.STA
t
SP
t
SP
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8
Functional Description
The device supports the I
2
C protocol. Any device that sends data on to the bus is defined to be a transmitter,
and any device that reads the data to a receiver. The device that controls the data transfer is known as the
bus master, and the other as the slave device.
1) Start Condition
A Start condition needs to start the EEPROM operation, it is to set falling edge of the SDA while the SCL
is stable in the high status.
2) Stop Condition
A Start condition is identified by rising edge of the SDA signal while the SCL is stable in the high status.
The device becomes the standby mode from a Read operation by a Stop condition. In a write sequence,
a stop condition is trigger to terminate the write data inputs and it is trigger to start the internal write cycle.
After the internally write cycle time which is specified as tWC, the device enters a standby mode.
3) Data Input
During data input, the device latches the SDA on the rising edge of the SCL. For correct the operation,
The SDA must be stable during the rising edge of the SCL.
Stop
condition
Start
condition
SCL
SDA
t
SU.STA
t
HD.STA
t
SU.STO
SCL
SDA
t
SU.DAT
t
HD.DAT
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9
4) Acknowledge Bit (ACK)
The Acknowledge Bit is used to indicate a successful byte data transfer. The receiver sends a zero to
acknowledge that it has received each word (Device Code, Slave Address etc) from the transmitter.
5) Device addressing
To transmit between the bus master and slave device (EEPROM), the master must send a Start condition
to the EEPROM. The device address word of the EEPROM consists of 4-bit Device Code, 3-bit Slave
Device address code and 1-bit read/write code. By sending these, it becomes possible to communicate
between the bus master and the EEPROM.
The upper 4-bit of the device address word are called the Device Code, the Device Code of the EEPROM
uses 1010b fixed code. This device has the 3-bit of the Slave Device address as the Slave address (S0,
S1, S2). The value of Slave address are fixed S0 = 0, S1 = 0, and S2 = 1.
When the Device Code is received on the SDA, the device only responds if Slave address pin tied to VDD
or VSS is the same as the Slave address signal input. The 8
th
bit is the read/write bit. The bit is set to 1 for
Read operation and 0 for Write operation. If a match occurs on the Device Code, the corresponding
device gives an acknowledgement on SDA during the 9
th
bit time. If device does not match the Device
Code, it deselects itself from the bus, and goes into the Standby mode. Use the Random Read command
when you execute reading after the slave device was switched.
1 0 1 0 S2 S1 S0 R/W
S2 = 1, S1 = 0, S0 = 0
Device Code
Slave
Address
MSB
LSB
Device address word
Acknowledge
Bit output
Start
condition
1
SCL
From Transmitter
SDA
(From Transmitter)
SDA
(EEPROM output)
8
9
t
AA
t
DH

LE2432RDXATDG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
EEPROM 32K BIT I2C FASTPLUS EEP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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