M29F200BB45N1 Datasheet M29F200BB45N1, M29F200BB50N3 | P10-P12

Signal descriptions M29F200BT, M29F200BB

10/39

2 Signal descriptions

See Figure 1: Logic diagram, and Table 1: Signal names, for a brief overview of the signals

connected to this device.

2.1 Address Inputs (A0-A16)

The Address Inputs select the cells in the memory array to access during Bus Read

operations. During Bus Write operations they control the commands sent to the Command

Interface of the internal state machine.

2.2 Data Inputs/Outputs (DQ0-DQ7)

The Data Inputs/Outputs output the data stored at the selected address during a Bus Read

operation. During Bus Write operations they represent the commands sent to the Command

Interface of the internal state machine.

2.3 Data Inputs/Outputs (DQ8-DQ14)

The Data Inputs/Outputs output the data stored at the selected address during a Bus Read

operation when BYTE

is High, V

. When BYTE is Low, V

, these pins are not used and are

high impedance. During Bus Write operations the Command Register does not use these

bits. When reading the Status Register these bits should be ignored.

2.4 Data Input/Output or Address Input (DQ15A-1)

When BYTE is High, V

, this pin behaves as a Data Input/Output pin (as DQ8-DQ14).

When BYTE

is Low, V

, this pin behaves as an address pin; DQ15A–1 Low will select the

LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout

the text consider references to the Data Input/Output to include this pin when BYTE

is High

and references to the Address Inputs to include this pin when BYTE

is Low except when

stated explicitly otherwise.

2.5 Chip Enable (E)

The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to

be performed. When Chip Enable is High, V

, all other pins are ignored.

2.6 Output Enable (G)

The Output Enable, G, controls the Bus Read operation of the memory.

M29F200BT, M29F200BB Signal descriptions

11/39

2.7 Write Enable (W)

The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.

2.8 Reset/Block Temporary Unprotect (RP)

The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the

memory or to temporarily unprotect all Blocks that have been protected.

A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, V

, for at

least t

PLPX

. After Reset/Block temporary unprotect goes High, V

, the memory will be ready

for Bus Read and Bus Write operations after t

PHEL

or t

RHEL

, whichever occurs last. See the

Ready/Busy Output section, Table 15: Reset/Block Temporary Unprotect AC Characteristics

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C) and Figure 11: Reset/Block Temporary

Unprotect ac waveforms, for more details.

Holding RP

at V

will temporarily unprotect the protected Blocks in the memory. Program

and Erase operations on all blocks will be possible. The transition from V

to V

must be

slower than t

PHPHH

2.9 Ready/Busy Output (RB)

The Ready/Busy pin is an open-drain output that can be used to identify when the memory

array can be read. Ready/Busy is high-impedance during Read mode, Auto Select mode

and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy

becomes high-impedance. See Table 15: Reset/Block Temporary Unprotect AC

Characteristics (TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C) and Figure 11: Reset/Block

Temporary Unprotect ac waveforms.

During Program or Erase operations Ready/Busy is Low, V

. Ready/Busy will remain Low

during Read/Reset commands or Hardware Resets until the memory is ready to enter Read

mode.

The use of an open-drain output allows the Ready/Busy pins from several memories to be

connected to a single pull-up resistor. A Low will then indicate that one, or more, of the

memories is busy.

2.10 Byte/Word Organization Select (BYTE)

The Byte/Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus

modes of the memory. When Byte/Word Organization Select is Low, V

, the memory is in 8-

bit mode, when it is High, V

, the memory is in 16-bit mode.

2.11 V

Supply Voltage

The V

Supply Voltage supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabled when the V

Supply Voltage is less than the Lockout

Voltage, V

LKO

. This prevents Bus Write operations from accidentally damaging the data

during power up, power down and power surges. If the Program/Erase Controller is

Signal descriptions M29F200BT, M29F200BB

12/39

programming or erasing during this time then the operation aborts and the memory contents

being altered will be invalid.

A 0.1µF capacitor should be connected between the V

Supply Voltage pin and the V

Ground pin to decouple the current surges from the power supply. The PCB track widths

must be sufficient to carry the currents required during program and erase operations, I

CC4

2.12 Vss Ground

The V

Ground is the reference for all voltage measurements.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39

M29F200BB45N1

Mfr. #:

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NOR Flash 256Kx8 or 128Kx16 45

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