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RT9715BGS

P1-P3P4-P6P7-P9P10-P11
Philips Semiconductors Product specification
PowerMOS transistor BUK100-50GL
Logic level TOPFET
Fig.14. Typical overload protection characteristics.
Conditions: V
DD
= 13 V; V
IS
= 5 V; SC load = 30 m
Ω
Fig.15. Typical clamping characteristics, 25 ˚C.
I
D
= f(V
DS
); conditions: V
IS
= 0 V; t
p
≤
50
µ
s
Fig.16. Input threshold voltage.
V
IS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= 5 V
Fig.17. Typical DC input characteristics.
I
IS
= f(V
IS
); normal operation, parameter: T
j
Fig.18. Typical DC input characteristics, T
j
= 25 ˚C.
I
ISL
= f(V
IS
); overload protection operated
⇒
I
D
= 0 A
Fig.19. Typical reverse diode current, T
j
= 25 ˚C.
I
S
= f(V
SDS
); conditions: V
IS
= 0 V; t
p
= 250
µ
s
-60 -20 20 60 100 140 180 220
Tmb / C
Energy & Time
BUK100-50GL
1
0.5
0
Energy / J
Time / ms
Tj(TO)
0 2 4 6 8 10
VIS / V
IIS / uA
BUK100-50GL
500
400
300
200
100
0
150 C
25 C
50 60 70
BUK100-50GL
VDS / V
ID / A
20
15
10
5
0
typ.
0 2 4 6 8
VIS / V
IISL / mA
BUK100-50GL
3
2
1
0
RESET
PROTECTION LATCHED
NORMAL
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
VIS(TO) / V
2
1
0
max.
typ.
min.
0 0.2 0.4 0.6 0.8 1 1.2 1.4
BUK100-50GL
VSD / V
IS / A
60
50
40
30
20
10
0
November 1996 7 Rev 1.300
Philips Semiconductors Product specification
PowerMOS transistor BUK100-50GL
Logic level TOPFET
Fig.20. Test circuit for resistive load switching times.
Fig.21. Typical switching waveforms, resistive load.
V
DD
= 13 V; R
L
= 4
Ω
; R
I
= 50
Ω
, T
j
= 25 ˚C.
Fig.22. Typical switching waveforms, resistive load.
V
DD
= 13 V; R
L
= 4
Ω
; R
I
= 50
Ω
, T
j
= 25 ˚C.
Fig.23. Test circuit for inductive load switching times.
Fig.24. Typical switching waveforms, inductive load.
V
DD
= 13 V; I
D
= 3 A; R
I
= 50
Ω
, T
j
= 25 ˚C.
Fig.25. Typical switching waveforms, inductive load.
V
DD
= 13 V; I
D
= 3 A; R
I
= 50
Ω
, T
j
= 25 ˚C.
VDD
D.U.T.
R
0V
0R1
I
VIS
ID measure
D
S
I
TOPFET
P
RL
: adjust for correct ID
VDD = VCL
LD
D.U.T.
R
0V
t
p
0R1
I
VIS
ID measure
D
S
I
TOPFET
P
0 10 20
RESISTIVE TURN-ON
time / us
BUK100-50GL
10
5
0
VDS / V
VIS / V
ID / A
10%
10%
td on
90%
tr
0 10 20
INDUCTIVE TURN-ON
time / us
BUK100-50GL
10
5
0
VDS / V
VIS / V
ID / A
10%
90%
10%
td on
tr
0 10 20
RESISTIVE TURN-OFF
time / us
BUK100-50GL
10
5
0
VDS / V
VIS / V
ID / A
90%
90%
10%
td off
tf
0 10 20
INDUCTIVE TURN-OFF
time / us
BUK100-50GL
15
10
5
0
VDS / V
VIS / V
ID / A
90%
90%
10%
td off tf
November 1996 8 Rev 1.300
Philips Semiconductors Product specification
PowerMOS transistor BUK100-50GL
Logic level TOPFET
Fig.26. Normalised limiting clamping energy.
E
DSM
% = f(T
mb
); conditions: I
D
= 15 A; V
IS
= 5 V
Fig.27. Clamping energy test circuit, R
IS
= 50
Ω
.
Fig.28. Typical off-state leakage current.
I
DSS
= f(T
j
); Conditions: V
DS
= 40 V; I
IS
= 0 V.
Fig.29. Normalised input current (normal operation).
I
IS
/I
IS
25 ˚C = f(T
j
); V
IS
= 5 V
Fig.30. Normalised input current (protection latched).
I
ISL
/I
ISL
25 ˚C = f(T
j
); V
IS
= 5 V
0 20 40 60 80 100 120 140
Tmb / C
EDSM%
120
110
100
90
80
70
60
50
40
30
20
10
0
-60 -20 20 60 100 140 180
Tj / C
Iiso normalised to 25 C
1.5
1
0.5
L
D.U.T.
VDD
RIS
R 01
VDS
-ID/100
+
-
shunt
VIS
0
P
D
S
I
TOPFET
ID
0
VDS
0
VDD
V(CL)DSS
Schottky
-60 -20 20 60 100 140 180
Tj / C
Iisl normalised to 25 C
1.5
1
0.5
E
DSM
= 0.5 ⋅LI
D
2
⋅V
(CL)DSS
/(V
(CL)DSS
−V
DD
)
0 20 40 60 80 100 120 140
Tj / C
Idss
1 mA
100 uA
10 uA
1 uA
100 nA
typ.
November 1996 9 Rev 1.300
P1-P3P4-P6P7-P9P10-P11

RT9715BGS

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IC PWR SW USB 2A 8SOP
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