Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. B
11/08/2011
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS61WV5128EDBLL
IS64WV5128EDBLL
FEATURES
• High-speed access time: 8, 10 ns
• Low Active Power: 85 mW (typical)
• Low Standby Power: 7 mW (typical)
CMOS standby
• Single power supply
— V
dd 2.4V to 3.6V (10 ns)
— V
dd 3.3V ± 10% (8 ns)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial and Automotive temperature support
• Lead-free available
• Error Detection and Error Correction
512K x 8 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH ECC
DESCRIPTION
The ISSI IS61/64WV5128EDBLL is a high-speed,
4,194,304-bit static RAMs organized as 524,288 words by
8 bits. It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with inno-
vative circuit design techniques, yields high-performance
and low power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be re-
duced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of
the memory.
The IS61/64WV5128EDBLL is packaged in the JEDEC
standard 44-pin TSOP-II, 36-pin SOJ and 36-pin Mini BGA
(6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
NOVEMBER 2011
Memory Array
(512Kx8)
ECC Array
(512Kx4)
Decoder
I/O Data
Circuit
ECC
Column I/O
8 8 12
8 4
Control
Circuit
/CE
/OE
/WE
IO0-7
A0-A18
