IS61WV5128EDBLL-10TLI

4 Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
11/08/2011
IS61/64WV5128EDBLL
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-8 -10 -20
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
iCC Vdd Dynamic Operating Vdd = Max., Com. 40 30 25 mA
Supply Current iOut = 0 mA, f = fmax Ind. 45 35 30
Auto. 50 45
typ.
(2)
21 21
iCC1 Operating Vdd = Max., Com. 20 20 20 mA
Supply Current iOut = 0 mA, f = 0 Ind. 25 25 25
Auto. 40 40
isb1 TTL Standby Current Vdd = Max., Com. 10 10 10 mA
(TTL Inputs) Vin = Vih or Vil Ind. 15 15 15
CE Vih, f = 0 Auto. 30 30
isb2 CMOS Standby Vdd = Max., Com. 5 5 5 mA
Current (CMOS Inputs) CE Vdd – 0.2V, Ind. 6 6 6
Vin Vdd – 0.2V, or Auto. 15 15
Vin 0.2V
, f = 0 typ.
(2)
1.5 1.5
Note:
1. At f = f
max, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at V
dd = 3.0V, Ta = 25
o
C and not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 2.4V-3.6V
Symbol Parameter Test Conditions Min. Max. Unit
VOh Output HIGH Voltage Vdd = Min., iOh = –1.0 mA 1.8 V
VOl Output LOW Voltage Vdd = Min., iOl = 1.0 mA 0.4 V
Vih Input HIGH Voltage 2.0 Vdd + 0.3 V
Vil Input LOW Voltage
(1)
–0.3 0.8 V
ili Input Leakage GND Vin Vdd
–1 1 µA
ilO Output Leakage
GND VOut Vdd, Outputs Disabled –1 1 µA
Note:
1.
Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V dC; Vih (max.) = Vdd + 2.0V aC (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 3.3V + 10%
Symbol Parameter Test Conditions Min. Max. Unit
VOh Output HIGH Voltage Vdd = Min., iOh = –4.0 mA 2.4 V
VOl Output LOW Voltage Vdd = Min., iOl = 8.0 mA 0.4 V
Vih Input HIGH Voltage 2 Vdd + 0.3 V
Vil Input LOW Voltage
(1)
–0.3 0.8 V
ili Input Leakage GND Vin Vdd
–1 1 µA
ilO Output Leakage
GND VOut Vdd, Outputs Disabled –1 1 µA
Note:
1.
Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V dC; Vih (max.) = Vdd + 2.0V aC (pulse width < 10 ns). Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com 5
Rev. B
11/08/2011
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IS61/64WV5128EDBLL
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-8 -10 -20
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
trC Read Cycle Time 8 10 20 ns
taa Address Access Time 8 10 20 ns
tOha Output Hold Time 2.0 2.0 2.5 ns
taCe CE Access Time 8 10 20 ns
tdOe OE Access Time 4.5 4.5 8 ns
thzOe
(2)
OE to High-Z Output 3 4 8 ns
tlzOe
(2)
OE to Low-Z Output 0 0 0 ns
thzCe
(2
CE to High-Z Output 0 3 0 4 0 8 ns
tlzCe
(2)
CE to Low-Z Output 3 3 3 ns
tPu Power Up Time 0 0 0 ns
tPd Power Down Time 8 10 20 ns
Notes:
1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
AC TEST LOADS
Figure 1.
319
5 pF
Including
jig and
scope
353
OUTPUT
3.3V
Figure 2.
Z
O
= 50
1.5V
50
OUTPUT
30 pF
Including
jig and
scope
AC TEST CONDITIONS
Parameter Unit
(2.4V-3.6V)
Input Pulse Level 0.4V to Vdd-0.3V
Input Rise and Fall Times 1V/ ns
Input and Output Timing Vdd/2
and Reference Level (VRef)
Output Load See Figures 1 and 2
6 Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
11/08/2011
IS61/64WV5128EDBLL
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z
DATA VALID
CE_RD2.eps
ADDRESS
OE
CE
D
OUT
t
HZCE
READ CYCLE NO. 2
(1,3)
(CE and OE Controlled)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE =
Vil.
3. Address is valid prior to or coincident with CE LOW transitions.
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
(Address Controlled) (CE = OE = Vil)

IS61WV5128EDBLL-10TLI

Mfr. #:
Manufacturer:
ISSI
Description:
SRAM 4Mb 2.4-3.6V 10ns 512x8 Async SRAM
Lifecycle:
New from this manufacturer.
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