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86004BGILF

P1-P3P4-P6P7-P9P10-P12P13-P13
15.625MHZ to 62.5MHZ, 1:4 LVCMOS/
LVTTL Zero Delay Clock Buffer
86004I
DATA SHEET
86004I REVISION A 7/10/15 1 ©2015 Integrated Device Technology, Inc.
GENERAL DESCRIPTION
The 86004I is a high performance 1:4 LVCMOS/LVTTL Clock Buffer.
The 86004I has a fully integrated PLL and can be confi gured as
zero delay buffer and has an input and output frequency range of
15.625MHz to 62.5MHz. The VCO operates at a frequency range
of 250MHz to 500MHz. The external feedback allows the device to
achieve “zero delay” between the input clock and the output clocks.
The PLL_SEL pin can be used to bypass the PLL for system test
and debug purposes. In bypass mode, the reference clock is routed
around the PLL and into the internal output divider.
FEATURES
• Four LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Single LVCMOS/LVTTL clock input
• CLK accepts the following input levels: LVCMOS or LVTTL
• Output frequency range: 15.625MHz to 62.5MHz
• Input frequency range: 15.625MHz to 62.5MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration
with confi gurable frequencies
• Fully integrated PLL
• Cycle-to-cycle jitter: 75ps (maximum)
• Output skew: 65ps (maximum)
• Full 3.3V or 2.5V, or 3.3V core/2.5V output operating supply
• -40°C to 85° ambient operating temperature
• Available in lead-free RoHS compliant package
BLOCK DIAGRAM PIN ASSIGNMENT
86004I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
15.625MHZ to 62.5MHZ, 1:4 LVCMOS/
LVTTL Zero Delay Clock Buffer
86004I DATA SHEET
2 REVISION A 7/10/15
Input
Output
F_SEL
0 Ref ÷8
1 Ref ÷16
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
TABLE 3A. CONTROL INPUT FUNCTION TABLE, PLL_SEL = 1
Input
Input/Output
Frequency Range (MHz)
F_SEL Minimum Maximum
0 31.25 62.5
1 15.625 31.25
TABLE 3B. CONTROL INPUT FUNCTION TABLE, PLL_SEL = 0
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51 kΩ
R
PULLDOWN
Input Pulldown Resistor 51 kΩ
C
PD
Power Dissipation Capacitance
(per output)
V
DD
, V
DDA
, V
DDO
= 3.465V 23 pF
V
DD
, V
DDA
, V
DDO
= 2.625V 17 pF
R
OUT
Output Impedance 3.3V ± 5% 5 7 12
Ω
Number Name Type Description
1, 3,
13, 15
Q1, Q0,
Q3, Q2
Output Clock outputs. 7Ω typical output impedance. LVCMOS/LVTTL interface levels.
2, 7, 14 GND Power Power supply ground.
4 F_SEL Input Pulldown
Frequency range select input. See Table 3A and 3B.
LVCMOS/LVTTL interface levels.
5V
DD
Power Core supply pin.
6 CLK Input Pulldown LVCMOS/LVTTL clock input.
8V
DDA
Power Analog supply pin.
9 PLL_SEL Input Pullup
Selects between the PLL and reference clock as input to the dividers.
When LOW, selects the reference clock (PLL Bypass). When HIGH,
selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.
10 FB_IN Input Pulldown
Feedback input to phase detector for regenerating clocks with “zero delay”.
Connect to one of the outputs. LVCMOS/LVTTL interface levels.
11 MR Input Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the outputs to go low. When logic LOW, the internal dividers and the
outputs are enabled. LVCMOS/LVTTL interface levels.
12, 16 V
DDO
Power Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
REVISION A 7/10/15
86004I DATA SHEET
3 15.625MHZ to 62.5MHZ, 1:4 LVCMOS/
LVTTL Zero Delay Clock Buffer
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = -40°C TO 85°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance, θ
JA
89°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 2.5V±5%, TA = -40°C TO 85°C
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, V
DD
= V
DDA
= V
DDO
= 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Core Supply Voltage 3.135 3.3 3.465 V
V
DDA
Analog Supply Voltage 3.135 3.3 V
DD
V
V
DDO
Output Supply Voltage 3.135 3.3 3.465 V
I
DD
Power Supply Current 98 mA
I
DDA
Analog Supply Current 22 mA
I
DDO
Output Supply Current 8mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Core Supply Voltage 3.135 3.3 3.465 V
V
DDA
Analog Supply Voltage 3.135 3.3 V
DD
V
V
DDO
Output Supply Voltage 2.375 2.5 2.625 V
I
DD
Power Supply Current 98 mA
I
DDA
Analog Supply Current 22 mA
I
DDO
Output Supply Current 8mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Core Supply Voltage 2.375 2.5 2.625 V
V
DDA
Analog Supply Voltage 2.375 2.5 V
DD
V
V
DDO
Output Supply Voltage 2.375 2.5 2.625 V
I
DD
Power Supply Current 88 mA
I
DDA
Analog Supply Current 18 mA
I
DDO
Output Supply Current 6mA
P1-P3P4-P6P7-P9P10-P12P13-P13

86004BGILF

Mfr. #:
Buy 86004BGILF
Manufacturer:
IDT
Description:
Clock Buffer 4 LVCMOS OUT ZDB
Lifecycle:
New from this manufacturer.
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