15.625MHZ to 62.5MHZ, 1:4 LVCMOS/
LVTTL Zero Delay Clock Buffer
86004I DATA SHEET
8 REVISION A 7/10/15
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 86004I provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL. V
DD
, V
DDA
and V
DDO
should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic V
DD
pin and also shows that V
DDA
requires that
an additional10Ω resistor along with a 10µF bypass capacitor be
connected to the V
DDA
pin.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10Ω
V
DDA
10 μF
.01μF
3.3V
.01μF
V
DD
INPUTS:
LVCMOS CONTROL PINS
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUTS
All unused LVCMOS output can be left fl oating. We recommend that
there is no trace attached.
FIGURE 2. 86004I SCHEMATIC EXAMPLE
SCHEMATIC EXAMPLE
Figure 2 shows a schematic example of using an 86004I. It is
recommended to have one decouple capacitor per power pin. Each
decoupling capacitor should be located as close as possible to the
power pin. The low pass fi lter R7, C11 and C16 for clean analog
supply should also be located as close to the V
DDA
pin as possible.
VDD
Ro ~ 7 Ohm
LVCMOS
R4
100
U1
ICS86004
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
Q1
GND
Q0
F_SEL
VDD
CLK
GND
VDDA PLL_SEL
FB_IN
MR
VDDO
Q3
GND
Q2
VDDO
VDD
R3
1K
C11
0.01u
R2 43
VDD
Zo = 50
Zo = 50
R11 43
Serial Termination
VDD
R6
1K
Zo = 50
(U1-12)
VDD
C2
0.1uF
(U1-5)
Zo = 50
VDD
C16
10u
VDD=3.3V
R8 43
Parallel Termination
Zo = 50
R7
10
R1 43
VDD
C3
0.1uF
(U1-16)
C1
0.1uF
R5
100
ICS86004I
