MAX194
14-Bit, 85ksps ADC with 10µA Shutdown
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Constraints on sequencing the four power supplies are
as follows.
• Apply VDDA before VDDD.
• Apply VSSA before VSSD.
• Apply AIN and REF after VDDA and VSSA are present.
• The power supplies should settle within the
MAX194’s power-on delay (minimum 500ns) or you
should recalibrate the converter (pulse RESET low)
before use.
Be sure that digital return currents do not pass through
the analog ground and that return-current paths are low
impedance. A 5mA current flowing through a PC board
ground trace impedance of only 0.1Ω creates an error
voltage of about 500µV, or about 1LSB error with a ±4V
full-scale system.
The board layout should ensure as much as possible
that digital and analog signal lines are kept separate.
Do not run analog and digital (especially clock) lines
parallel to one another. If you must cross one with the
other, do so at right angles.
The ADC’s high-speed comparator is sensitive to high-
frequency noise on the VDDA and VSSA power sup-
plies. Bypass these supplies to the analog ground
plane with 0.1µF in parallel with 1µF or 10µF low-ESR
capacitors. Keep capacitor leads short for best supply-
noise rejection.
Shutdown
The MAX194 may be shut down by pulling BP/UP/
SHDN low. In addition to lowering power dissipation to
10µW (100µW max) when the device is not in use, con-
siderable power savings is possible by shutting the
converter down for short periods between conversions.
There is no need to perform a reset (calibration) after
the converter has been shut down unless the time in
shutdown is long enough that the supply voltages or
ambient temperature may have changed.
The time required for the converter to “wake up” and
settle depends heavily on the amount of additional error
acceptable. For 0.1LSB additional error, 3.2µs is suffi-
cient settling time and also allows enough time for reac-
quisition of the analog input signal. 20µs settling is
required for less than 0.05LSB error. Figure 23 is a
Figure 21. MAX194 Code Listing for 68HC16 Module and Circuit of Figure 19 (continued)
